Lines Matching +full:no +full:- +full:eeprom

1 /*-
2  * SPDX-License-Identifier: ISC
4  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5  * Copyright (c) 2002-2008 Atheros Communications, Inc.
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
25  * EEPROM defines for Version 1 Crete EEPROM.
27  * The EEPROM is segmented into three sections:
30  *    Cardbus CIS tuples and vendor-specific data
31  *    Atheros-specific data
33  * EEPROM entries are read 32-bits at a time through the PCI bus
34  * interface but are all 16-bit values.
36  * Access to the Atheros-specific data is controlled by protection
38  * data from the EEPROM at attach and caches it in its private state.
40  * settings, and phy-related configuration settings.
42 #define	AR_EEPROM_MAC(i)	(0x1f-(i))/* MAC address word */
47 #define AR_EEPROM_ATHEROS_BASE	0xc0	/* Base of Atheros-specific data */
48 #define AR_EEPROM_ATHEROS_MAX	64	/* 64x2=128 bytes of EEPROM settings */
55 #define AR_TP_SCALING_ENTRIES	11	/* # entries in transmit power dBm->pcdac */
82  * Information retrieved from EEPROM.
86 	uint16_t	ee_protect;		/* EEPROM protect field */