Lines Matching full:inbound
277 /* message code of inbound message register */
393 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready…
481 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 /* inbound message 0 ready */
498 //set host rw buffer physical address at inbound message 0, 1 (low,high)
608 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
616 …u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consu…
617 …u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consu…
637 …u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port l…
638 …u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port h…
752 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
781 …u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port l…
782 …u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port h…
830 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/
859 …u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port l…
860 …u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port h…
928 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331)
936 ** (inbound queue port) Request frame must be 32 bytes aligned
980 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to I…
988 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver …
1001 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound messa…
1002 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Stat…
1007 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop)
1025 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver…
1033 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuff…
1047 ** inbound doorbell : at offset 0x20
1048 ** inbound doorbell clear : at offset 0x70
1050 ** inbound doorbell : bit0 -- reserved
1053 ** bit3 -- inbound message 0 ready
1068 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code ms…
1072 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43
1073 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper)
1080 ** to post inbound request in a single instruction, and use 64bit instruction
1082 ** If in 32bit environment, when sending inbound queue, write high part first
1370 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */
2657 ** | Inbound ATU Base Address 0 …
2659 ** | Inbound ATU Upper Base Address 0 …
2661 ** | Inbound ATU Base Address 1 …
2663 ** | Inbound ATU Upper Base Address 1 …
2665 ** | Inbound ATU Base Address 2 …
2667 ** | Inbound ATU Upper Base Address 2 …
2748 ** �E Write Data Parity Error when the ATU is a target (inbound write).
2875 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines t…
2876 …* Inbound ATU Upper Base Address Register 0 N/A Together …
2877 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines i…
2878 ** Inbound ATU Upper Base Address Register 1 N/A Together …
2879 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines t…
2880 …* Inbound ATU Upper Base Address Register 2 N/A Together …
2881 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines t…
2882 …* Inbound ATU Upper Base Address Register 3 N/A Together …
2886 ** ATU Inbound Window 1 is not a translate window.
2895 ** Inbound ATU Base Address Register 0 - IABAR0
2897 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Add…
2898 ** defines the block of memory addresses where the inbound translation window 0 begins.
2899 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a transla…
2936 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0
2954 ** Inbound ATU Base Address Register 1 - IABAR1
2956 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Addre…
2957 ** defines the block of memory addresses where the inbound translation window 1 begins.
2990 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1
3012 ** Inbound ATU Base Address Register 2 - IABAR2
3014 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Add…
3015 ** defines the block of memory addresses where the inbound translation window 2 begins.
3016 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a transla…
3051 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2
3121 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0
3208 ** Inbound Address Translation
3212 ** The process of inbound address translation involves two steps:
3215 ** within the address windows defined for the inbound ATU.
3220 ** The ATU uses the following registers in inbound address window 0 translation:
3221 ** �E Inbound ATU Base Address Register 0
3222 ** �E Inbound ATU Limit Register 0
3223 ** �E Inbound ATU Translate Value Register 0
3224 ** The ATU uses the following registers in inbound address window 2 translation:
3225 ** �E Inbound ATU Base Address Register 2
3226 ** �E Inbound ATU Limit Register 2
3227 ** �E Inbound ATU Translate Value Register 2
3228 ** The ATU uses the following registers in inbound address window 3 translation:
3229 ** �E Inbound ATU Base Address Register 3
3230 ** �E Inbound ATU Limit Register 3
3231 ** �E Inbound ATU Translate Value Register 3
3232 ** Note: Inbound Address window 1 is not a translate window.
3234 ** Inbound Address window 3 does not reside in the standard section of the configuration h…
3239 ** Inbound address detection is determined from the 32-bit PCI address,
3245 ** Equation 1. Inbound Address Detection
3247 ** the PCI Address is claimed by the Inbound ATU.
3250 ** with the associated inbound limit register.
3252 ** the inbound PCI address is detected as being within the inbound translation window …
3254 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for …
3261 ** Equation 2. Inbound Translation
3266 ** the result is the internal bus address. This translation mechanism is used for all inbound m…
3267 ** read and write commands excluding inbound configuration read and writes.
3268 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear
3276 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes)
3283 ** ANS: PCI_Address is in the Inbound Translation Window
3295 ** Inbound ATU Limit Register 0 - IALR0
3297 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI
3312 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value deter…
3313 … inbound memory window 0 of the address translation unit. This de…
3320 ** Inbound ATU Translate Value Register 0 - IATVR0
3322 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to
3324 ** inbound ATU address translation.
3327 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to…
3369 ** Inbound ATU Limit Register 1 - IALR1
3378 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does
3384 ** 31:12 00000H Inbound Translation Limit 1 - This readback value deter…
3392 ** Inbound ATU Limit Register 2 - IALR2
3394 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI
3397 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When
3414 ** 31:12 00000H Inbound Translation Limit 2 - This readback value deter…
3422 ** Inbound ATU Translate Value Register 2 - IATVR2
3424 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to
3426 ** inbound ATU address translation.
3429 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to…
3620 ** Inbound Transaction Queue Busy:
3621 ** 0=Inbound Transaction Queue Empty
3622 ** 1=Inbound Transaction Queue Busy
3677 ** (Inbound Read Request). For a cleaner
3681 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueue…
3682 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) T…
3686 ** however the user is now assured that the ATU no longer has any pending inbound or outbound spl…
3688 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is
3747 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is …
3761 ** �E Write Data Parity Error when the ATU is a target (inbound write).
3805 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Control…
3849 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU …
3851 ** inbound write transaction.
3856 ** during an inbound read transaction where the data phase that was target aborted on the int…
3857 ** actually requested from the inbound read queue.
3869 ** Inbound ATU Base Address Register 3 - IABAR3
3871 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Add…
3872 ** of memory addresses where the inbound translation window 3 begins.
3873 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a transla…
3911 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3
3931 ** Inbound ATU Limit Register 3 - IALR3
3933 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI
3936 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When
3953 ** 31:12 00000H Inbound Translation Limit 3 - This readback value deter…
3961 ** Inbound ATU Translate Value Register 3 - IATVR3
3963 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to
3965 ** inbound ATU address translation.
3968 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to…
4270 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound…
4316 ** Inbound Read Transaction
4318 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local
4320 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue
4322 ** When operating in the conventional PCI mode, all inbound read transactions are processed as
4323 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are
4326 ** an inbound read transaction on the PCI bus is summarized in the following statements:
4327 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound
4328 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base
4329 ** Address Register during DACs) and Inbound Limit Register.
4398 ** The data flow for an inbound read transaction on the internal bus is summarized in the following
4436 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue
4449 ** Inbound Write Transaction
4451 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local
4453 ** Data flow for an inbound write transaction on the PCI bus is summarized as:
4454 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound
4455 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper
4456 ** Base Address Register during DACs) and Inbound Limit Register.
4469 ** for details of the inbound write data parity error response.
4472 ** interface becomes aware of the inbound write. When there are additional write transactions ahe…
4483 ** Data flow for the inbound write transaction on the internal bus is summarized as:
4487 ** transaction by driving the translated address onto the internal bus. For details on inbound
4523 ** Inbound Read Completions Data Parity Errors
4534 ** Inbound Configuration Write Completion Message Data Parity Errors
4545 ** Inbound Read Request Data Parity Errors
4548 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as havi…
4554 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may
4562 ** Inbound Write Request Data Parity Errors
4581 ** Inbound Configuration Write Request
4589 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following
4596 ** inbound transactions during Delayed Write Request cycles with the given constraints:
4690 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translatio…
4692 ** 1.Inbound ATU Base Address Register 0 (IABAR0)
4693 ** 2.Inbound ATU Limit Register 0 (IALR0)
4701 ** Message Registers 2 Inbound Optional Option…
4704 ** Doorbell Registers 1 Inbound Optional Option…
4711 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space
4718 ** 0010H Inbound Message Register 0 ]
4719 ** 0014H Inbound Message Register 1 ]
4723 ** 0020H Inbound Doorbell Register ]
4724 ** 0024H Inbound Interrupt Status Register ]
4725 ** 0028H Inbound Interrupt Mask Register ]
4733 ** 0040H Inbound Queue Port ]
4770 ** Two queues are used for inbound messages and two are used for outbound messages.
4776 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and…
4791 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation …
4793 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Addr…
4804 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert …
4813 ** . Inbound messages are sent by the host processor and received by the 80331.
4816 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register.
4818 ** Inbound Messages:
4820 ** . When an inbound message register is written by an external PCI agent, an interrupt may be gen…
4821 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register.
4822 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register.
4823 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Sta…
4826 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register.
4828 ** Inbound Message Register - IMRx
4830 ** . There are two Inbound Message Registers: IMR0 and IMR1.
4832 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked
4833 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register.
4836 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by a…
4863 ** Inbound Doorbell Register
4865 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R …
4869 ** Inbound Doorbells:
4871 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be g…
4874 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI …
4875 ** The interrupt is recorded in the Inbound Interrupt Status Register.
4876 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interru…
4878 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit …
4879 ** and not the values written to the Inbound Doorbell Register.
4880 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt.
4881 …ared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register…
4884 ** Inbound Doorbell Register - IDR
4886 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core.
4890 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound In…
4902 ** Inbound Interrupt Status Register - IISR
4904 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status.
4909 ** The generation of interrupts recorded in the Inbound Interrupt Status Register
4910 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register.
4921 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware …
4925 ** software must retain the information that the Inbound Post queue s…
4927 …ror Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register…
4928 … To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register…
4929 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one
4930 ** Normal Interrupt bit in the Inbound Doorbell Register is set.
4931 … To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register…
4932 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware w…
4933 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware w…
4946 ** Inbound Interrupt Mask Register - IIMR
4948 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core int…
4949 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status…
4950 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Regist…
4959 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the in…
4960 ** by the MU hardware when the Inbound Post Queue has been written.
4962 ** when the Error Interrupt bit of the Inbound Doorbell Register is set.
4963 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the inte…
4964 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set.
4965 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inb…
4966 ** Interrupt generated by a write to the Inbound Message 1 Register.
4967 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set,
4968 … this bit masks the Inbound Message 0 Interrupt generated by a write to t…
5082 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In
5083 ** this case, inbound and outbound refer to the direction of the flow of posted messages.
5084 ** Inbound messages are either:
5090 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow towar…
5092 ** . The two inbound queues are used to handle inbound messages
5094 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages…
5095 ** The other inbound queue is designated the Post queue and it contains inbound posted messages.
5103 ** |Inbound Post Queue | Queue for inbound messages from other processors | …
5105 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | …
5113 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one
5115 ** The host processor posts inbound messages,
5117 ** places it back on the inbound free queue for reuse by the host processor.
5121 ** Inbound Queue Port
5123 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write …
5125 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/…
5128 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface.
5163 ** Inbound Free Queue QBAR
5164 ** Inbound Post Queue QBAR + Queue Size
5168 ** Inbound Post Queue
5170 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XSc…
5173 ** For a PCI write transaction that accesses the Inbound Queue Port,
5174 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Re…
5175 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware inc…
5176 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written.
5177 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the int…
5178 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared.
5179 ** The interrupt can be masked by the Inbound Interrupt Mask Register.
5180 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee
5185 ** Only a new message posting the in the inbound queue generates a new interrupt.
5187 ** software must retain the information that the Inbound Post queue status.
5189 ** in local memory and the Inbound Post Head Pointer Register is incremented,
5190 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry.
5191 ** The Intel XScale core may read messages from the Inbound Post Queue
5192 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer …
5193 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register.
5194 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was …
5198 ** Inbound Free Queue
5200 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for ot…
5205 ** For a PCI read transaction that accesses the Inbound Queue Port,
5206 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer.
5212 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register.
5213 …d access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue.
5214 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an i…
5220 ** and the Inbound Free Head Pointer Register is written.
5221 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messa…
5223 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue …
5224 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the
5225 ** local memory location pointed to by the Inbound Free Head Pointer Register.
5226 ** The processor must then increment the Inbound Free Head Pointer Register.
5276 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound F…
5278 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the
5295 ** |Inbound Post | Inbound Queue | | | …
5298 ** |Inbound Free | Inbound Queue | | | …
5307 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by soft…
5309 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hard…
5319 ** These registers are for inbound messages only.
5320 ** The interrupt is recorded in the Inbound Interrupt Status Register.
5324 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Registe…
5325 ** to Inbound ATU Translate Value Registe…
5329 ** Interrupt bit in the Inbound Interrupt Status Register is cleared.
5344 ** FFFF E310H Inbound Message Register 0 | Available through
5345 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation…
5348 ** FFFF E320H Inbound Doorbell Register |
5349 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI addr…
5350 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core
5365 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core
5366 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address
5367 ** FFFF E368H Inbound Post Head pointer Register |
5368 ** FFFF E36CH Inbound Post Tail Pointer Register |
5432 ** Inbound Free Head Pointer Register - IFHPR
5434 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from
5435 ** the Queue Base Address of the head pointer for the Inbound Free Queue.
5443 … 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head poi…
5450 ** Inbound Free Tail Pointer Register - IFTPR
5452 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue
5453 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned…
5459 … 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail poi…
5466 ** Inbound Post Head Pointer Register - IPHPR
5468 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue
5469 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned…
5475 … 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head poi…
5482 ** Inbound Post Tail Pointer Register - IPTPR
5484 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue
5485 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned…
5491 … 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail poi…
5502 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Reg…
5504 ** by adding the Index Address Register to the Inbound ATU Translate Value Register.