Lines Matching +full:0 +full:xfff7
93 static int msi_disable = 0;
99 * set this to 0 or 1 to override the default.
113 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" },
115 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" },
119 "Atheros AR8152 v2.0 PCIe Fast Ethernet" },
134 { 0, 0, 0, NULL}
246 DRIVER_MODULE(alc, pci, alc_driver, 0, 0);
249 DRIVER_MODULE(miibus, alc, miibus_driver, 0, 0);
252 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
253 { -1, 0, 0 }
257 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
258 { -1, 0, 0 }
263 { -1, 0, 0 }
268 { -1, 0, 0 }
271 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 };
280 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
299 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 &&
301 return (0);
305 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
308 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
312 if (i == 0) {
314 return (0);
326 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
332 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
335 if ((v & MDIO_OP_BUSY) == 0)
339 if (i == 0) {
341 return (0);
354 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
370 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
373 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
377 if (i == 0)
380 return (0);
389 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
396 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
399 if ((v & MDIO_OP_BUSY) == 0)
403 if (i == 0)
406 return (0);
422 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
434 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
445 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
453 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active));
485 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
491 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
494 if ((v & MDIO_OP_BUSY) == 0)
498 if (i == 0) {
501 return (0);
515 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
522 for (i = ALC_PHY_TIMEOUT; i > 0; i--) {
525 if ((v & MDIO_OP_BUSY) == 0)
529 if (i == 0)
533 return (0);
541 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
550 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
576 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
596 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
616 if ((if_getflags(ifp) & IFF_UP) == 0) {
693 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
706 eeprom = 0;
708 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
709 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
718 if ((opt & OPT_CFG_CLK_ENB) == 0) {
730 ALC_MII_DBG_ADDR, 0x00);
734 ALC_MII_DBG_DATA, val & 0xFF7F);
736 ALC_MII_DBG_ADDR, 0x3B);
740 ALC_MII_DBG_DATA, val | 0x0008);
747 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
752 for (i = 100; i > 0; i--) {
755 TWSI_CFG_SW_LD_START) == 0)
758 if (i == 0)
765 if (eeprom != 0) {
769 if ((opt & OPT_CFG_CLK_ENB) != 0) {
781 ALC_MII_DBG_ADDR, 0x00);
785 ALC_MII_DBG_DATA, val | 0x0080);
787 ALC_MII_DBG_ADDR, 0x3B);
791 ALC_MII_DBG_DATA, val & 0xFFF7);
806 reloaded = 0;
808 for (i = 100; i > 0; i--) {
810 if ((reg & (SLD_PROGRESS | SLD_START)) == 0)
814 if (i != 0) {
816 for (i = 100; i > 0; i--) {
819 if ((reg & SLD_START) == 0)
822 if (i != 0)
830 if (reloaded == 0) {
833 EEPROM_LD_FLASH_EXIST)) != 0) {
834 for (i = 100; i > 0; i--) {
837 EEPROM_LD_START)) == 0)
841 if (i != 0) {
844 for (i = 100; i > 0; i--) {
847 if ((reg & EEPROM_LD_START) == 0)
864 ea[0] = CSR_READ_4(sc, ALC_PAR0);
866 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
867 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
868 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
869 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
870 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
871 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
879 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
895 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
919 ALC_MII_DBG_ADDR, 0x000A);
923 ALC_MII_DBG_DATA, data & 0xDFFF);
930 ALC_MII_DBG_ADDR, 0x003B);
934 ALC_MII_DBG_DATA, data & 0xFFF7);
939 ALC_MII_DBG_ADDR, 0x0029);
941 ALC_MII_DBG_DATA, 0x929D);
948 ALC_MII_DBG_ADDR, 0x0029);
950 ALC_MII_DBG_DATA, 0xB6DD);
999 0x0029);
1002 data &= ~0x8000;
1007 0x000B);
1010 data &= ~0x8000;
1055 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0);
1072 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) {
1114 * GPHY power down caused more problems on AR8151 v2.0.
1118 * AR8151 v1.0 also requires this one though. I don't
1119 * have AR8151 v1.0 controller in hand.
1141 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
1153 if ((sc->alc_flags & ALC_FLAG_LINK) == 0)
1162 linkcfg = 0;
1169 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
1170 /* Disable extended sync except AR8152 B v1.0 */
1187 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1188 if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
1190 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1192 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
1229 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1254 (sc->alc_rev & 0x01) != 0)
1256 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1261 if (init != 0)
1264 else if ((if_getdrvflags(sc->alc_ifp) & IFF_DRV_RUNNING) != 0)
1282 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
1299 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1301 if ((ctl & PCIEM_LINK_CTL_RCB) != 0)
1314 state == 0 ? "disabled" : "enabled");
1327 (sc->alc_rev & 0x01) != 0) {
1328 if ((val & MASTER_WAKEN_25M) == 0 ||
1329 (val & MASTER_CLK_SEL_DIS) == 0) {
1334 if ((val & MASTER_WAKEN_25M) == 0 ||
1335 (val & MASTER_CLK_SEL_DIS) != 0) {
1350 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
1361 if (mod == 0)
1364 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1367 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1371 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0);
1383 error = 0;
1390 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0);
1391 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc);
1399 if (error != 0) {
1430 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0)
1462 msix_disable = 0;
1480 device_printf(dev, "PCI device revision : 0x%04x\n",
1482 device_printf(dev, "Chip id/revision : 0x%04x\n",
1484 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
1485 device_printf(dev, "AR816x revision : 0x%x\n",
1493 sc->alc_dma_rd_burst = 0;
1494 sc->alc_dma_wr_burst = 0;
1496 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) {
1519 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0)
1520 sc->alc_dma_wr_burst = 0;
1548 if (msix_disable == 0 || msi_disable == 0) {
1549 if (msix_disable == 0 && msixc > 0 &&
1550 pci_alloc_msix(dev, &msixc) == 0) {
1559 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 &&
1560 msic > 0 && pci_alloc_msi(dev, &msic) == 0) {
1572 if (error != 0) {
1580 if ((error = alc_dma_alloc(sc)) != 0)
1597 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) {
1598 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0);
1608 if (error != 0) {
1617 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
1631 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
1632 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM);
1633 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES);
1646 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1648 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1652 for (i = 0; i < msic; i++) {
1656 if (error != 0)
1659 if (error != 0) {
1671 if (error != 0)
1710 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0)
1712 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1716 for (i = 0; i < msic; i++) {
1723 if (sc->alc_res[0] != NULL)
1726 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0)
1731 return (0);
1735 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
1754 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation");
1757 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation");
1762 if (error == 0) {
1774 if (error == 0) {
1785 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I",
1792 if (error == 0) {
1928 if (error != 0)
1934 ctx->alc_busaddr = segs[0].ds_addr;
1970 return (0);
1989 1, 0, /* alignment, boundary */
1994 0, /* nsegments */
1996 0, /* flags */
1999 if (error != 0) {
2008 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */
2015 0, /* flags */
2018 if (error != 0) {
2027 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */
2034 0, /* flags */
2037 if (error != 0) {
2045 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */
2052 0, /* flags */
2055 if (error != 0) {
2064 ALC_CMB_ALIGN, 0, /* alignment, boundary */
2071 0, /* flags */
2074 if (error != 0) {
2082 ALC_SMB_ALIGN, 0, /* alignment, boundary */
2089 0, /* flags */
2092 if (error != 0) {
2103 if (error != 0) {
2108 ctx.alc_busaddr = 0;
2111 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0);
2112 if (error != 0 || ctx.alc_busaddr == 0) {
2124 if (error != 0) {
2129 ctx.alc_busaddr = 0;
2132 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0);
2133 if (error != 0 || ctx.alc_busaddr == 0) {
2145 if (error != 0) {
2150 ctx.alc_busaddr = 0;
2153 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0);
2154 if (error != 0 || ctx.alc_busaddr == 0) {
2166 if (error != 0) {
2171 ctx.alc_busaddr = 0;
2174 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0);
2175 if (error != 0 || ctx.alc_busaddr == 0) {
2187 if (error != 0) {
2192 ctx.alc_busaddr = 0;
2195 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0);
2196 if (error != 0 || ctx.alc_busaddr == 0) {
2205 (error = alc_check_boundary(sc)) != 0) {
2226 1, 0, /* alignment, boundary */
2231 0, /* nsegments */
2233 0, /* flags */
2236 if (error != 0) {
2245 1, 0, /* alignment, boundary */
2252 0, /* flags */
2255 if (error != 0) {
2263 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */
2270 0, /* flags */
2273 if (error != 0) {
2278 for (i = 0; i < ALC_TX_RING_CNT; i++) {
2282 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0,
2284 if (error != 0) {
2291 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
2292 &sc->alc_cdata.alc_rx_sparemap)) != 0) {
2297 for (i = 0; i < ALC_RX_RING_CNT; i++) {
2301 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0,
2303 if (error != 0) {
2323 for (i = 0; i < ALC_TX_RING_CNT; i++) {
2336 for (i = 0; i < ALC_RX_RING_CNT; i++) {
2354 if (sc->alc_rdata.alc_tx_ring_paddr != 0)
2361 sc->alc_rdata.alc_tx_ring_paddr = 0;
2368 if (sc->alc_rdata.alc_rx_ring_paddr != 0)
2375 sc->alc_rdata.alc_rx_ring_paddr = 0;
2382 if (sc->alc_rdata.alc_rr_ring_paddr != 0)
2389 sc->alc_rdata.alc_rr_ring_paddr = 0;
2396 if (sc->alc_rdata.alc_cmb_paddr != 0)
2403 sc->alc_rdata.alc_cmb_paddr = 0;
2410 if (sc->alc_rdata.alc_smb_paddr != 0)
2417 sc->alc_rdata.alc_smb_paddr = 0;
2463 aneg = 0;
2477 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0);
2483 if (aneg != 0) {
2487 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
2522 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
2539 if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
2541 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2552 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
2553 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
2559 pmcs = 0;
2560 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
2566 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
2568 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2575 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) {
2585 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2607 if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
2608 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2612 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
2614 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
2617 pmcs = 0;
2618 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
2624 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
2626 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2645 if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
2650 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2669 return (0);
2682 if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
2686 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2695 if ((if_getflags(ifp) & IFF_UP) != 0) {
2696 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2701 return (0);
2724 ip_off = poff = 0;
2725 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) {
2736 if (M_WRITABLE(m) == 0) {
2774 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2801 ip->ip_sum = 0;
2814 *m_head, txsegs, &nsegs, 0);
2824 *m_head, txsegs, &nsegs, 0);
2825 if (error != 0) {
2830 } else if (error != 0)
2832 if (nsegs == 0) {
2847 vtag = 0;
2849 idx = 0;
2851 if ((m->m_flags & M_VLANTAG) != 0) {
2856 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2873 desc->addr = htole64(txsegs[0].ds_addr);
2876 if (m->m_len - hdrlen > 0) {
2882 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
2888 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) {
2899 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
2901 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
2903 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2933 return (0);
2963 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0)
2966 for (enq = 0; !if_sendq_empty(ifp); ) {
2979 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
2991 if (enq > 0)
3003 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3022 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer)
3026 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
3029 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3035 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3051 error = 0;
3057 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 &&
3065 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) {
3066 if_setcapenablebit(ifp, 0, IFCAP_TSO4);
3067 if_sethwassistbits(ifp, 0, CSUM_TSO);
3075 if ((if_getflags(ifp) & IFF_UP) != 0) {
3076 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 &&
3078 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3082 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
3090 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
3102 if ((mask & IFCAP_TXCSUM) != 0 &&
3103 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
3105 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
3106 if_sethwassistbits(ifp, ALC_CSUM_FEATURES, 0);
3108 if_sethwassistbits(ifp, 0, ALC_CSUM_FEATURES);
3110 if ((mask & IFCAP_TSO4) != 0 &&
3111 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
3113 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) {
3116 if_setcapenablebit(ifp, 0, IFCAP_TSO4);
3117 if_sethwassistbits(ifp, 0, CSUM_TSO);
3119 if_sethwassistbits(ifp, CSUM_TSO, 0);
3121 if_sethwassistbits(ifp, 0, CSUM_TSO);
3123 if ((mask & IFCAP_WOL_MCAST) != 0 &&
3124 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0)
3126 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3127 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
3129 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3130 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
3134 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
3135 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
3137 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3138 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
3140 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
3141 if_setcapenablebit(ifp, 0,
3166 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
3181 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
3183 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
3185 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
3198 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3204 smb->updated = 0;
3209 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
3215 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
3236 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3241 if (smb->updated == 0)
3246 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered;
3252 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes;
3330 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
3332 smb->updated = 0;
3353 if ((status & ALC_INTRS) == 0)
3375 if (sc->alc_morework != 0) {
3376 sc->alc_morework = 0;
3379 if ((status & ALC_INTRS) == 0)
3385 more = 0;
3386 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
3387 if ((status & INTR_RX_PKT) != 0) {
3392 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3399 INTR_TXQ_TO_RST)) != 0) {
3400 if ((status & INTR_DMA_RD_TO_RST) != 0)
3403 if ((status & INTR_DMA_WR_TO_RST) != 0)
3406 if ((status & INTR_TXQ_TO_RST) != 0)
3409 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3414 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 &&
3420 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) {
3427 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
3430 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
3432 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
3448 if (sc->alc_cdata.alc_tx_cnt == 0)
3452 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
3457 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3472 if (sc->alc_cdata.alc_tx_cnt <= 0)
3474 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
3488 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
3496 if (sc->alc_cdata.alc_tx_cnt == 0)
3497 sc->alc_watchdog_timer = 0;
3517 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3534 rxd->rx_desc->addr = htole64(segs[0].ds_addr);
3535 return (0);
3553 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;) {
3554 if (count-- <= 0)
3558 if ((status & RRD_VALID) == 0)
3561 if (nsegs == 0) {
3569 rrd->status = 0;
3576 if (prog > 0) {
3599 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
3607 return (count > 0 ? 0 : EAGAIN);
3622 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
3665 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) {
3680 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0)
3684 for (count = 0; count < nsegs; count++,
3689 if (alc_newbuf(sc, rxd) != 0) {
3748 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
3749 (status & RRD_VLAN_TAG) != 0) {
3839 pmcfg = 0;
3840 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3844 (sc->alc_rev & 0x01) != 0) {
3848 != 0) {
3859 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3860 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3862 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)
3865 if (i == 0)
3868 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3870 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
3873 if (i == 0)
3876 for (i = ALC_RESET_TIMEOUT; i > 0; i--) {
3879 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
3883 if (i == 0)
3884 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg);
3886 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3888 (sc->alc_rev & 0x01) != 0) {
3894 != 0)
3910 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
3941 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
3953 if (alc_init_rx_ring(sc) != 0) {
3964 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3973 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
3979 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
3985 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
3991 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
3999 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4001 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
4002 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
4003 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
4029 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4031 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
4032 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
4033 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
4046 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
4047 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
4048 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
4049 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
4050 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
4051 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
4052 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
4053 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
4061 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0)
4071 if (ALC_USECS(sc->alc_int_rx_mod) != 0)
4073 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 &&
4074 ALC_USECS(sc->alc_int_tx_mod) != 0)
4081 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
4083 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4088 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
4092 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
4100 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
4120 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4122 CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
4153 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
4166 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4192 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4219 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4221 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
4222 CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
4229 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4233 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
4236 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 &&
4245 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
4247 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
4259 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
4290 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
4295 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
4307 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4308 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
4310 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
4311 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4334 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
4337 sc->alc_watchdog_timer = 0;
4340 CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
4341 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4351 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
4353 alc_aspm(sc, 0, IFM_UNKNOWN);
4361 for (i = 0; i < ALC_RX_RING_CNT; i++) {
4372 for (i = 0; i < ALC_TX_RING_CNT; i++) {
4394 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
4398 for (i = ALC_TIMEOUT; i > 0; i--) {
4400 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0)
4404 if (i == 0)
4406 "could not disable Rx/Tx MAC(0x%08x)!\n", reg);
4413 0,
4425 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4445 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
4446 if ((reg & RXQ_CFG_ENB) != 0) {
4451 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) {
4458 if ((reg & TXQ_CFG_ENB) != 0) {
4463 for (i = ALC_TIMEOUT; i > 0; i--) {
4465 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0)
4469 if (i == 0)
4471 "could not disable RxQ/TxQ (0x%08x)!\n", reg);
4483 sc->alc_cdata.alc_tx_prod = 0;
4484 sc->alc_cdata.alc_tx_cons = 0;
4485 sc->alc_cdata.alc_tx_cnt = 0;
4489 for (i = 0; i < ALC_TX_RING_CNT; i++) {
4508 sc->alc_morework = 0;
4511 for (i = 0; i < ALC_RX_RING_CNT; i++) {
4515 if (alc_newbuf(sc, rxd) != 0)
4529 return (0);
4539 sc->alc_cdata.alc_rr_cons = 0;
4585 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
4599 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
4618 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
4620 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
4621 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
4623 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0)
4625 mchash[0] = 0xFFFFFFFF;
4626 mchash[1] = 0xFFFFFFFF;
4633 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
4646 error = sysctl_handle_int(oidp, &value, 0, req);
4653 return (0);
4702 if (error == 0)