Lines Matching +full:0 +full:x1800000
96 } while (0)
101 #define PCI_VENDOR_ID_ANNAPURNA_LABS 0x1c36
102 #define PCI_DEVICE_ID_AL_ETH 0x0001
103 #define PCI_DEVICE_ID_AL_ETH_ADVANCED 0x0002
104 #define PCI_DEVICE_ID_AL_ETH_NIC 0x0003
105 #define PCI_DEVICE_ID_AL_ETH_FPGA_NIC 0x0030
106 #define PCI_DEVICE_ID_AL_CRYPTO 0x0011
107 #define PCI_DEVICE_ID_AL_CRYPTO_VF 0x8011
108 #define PCI_DEVICE_ID_AL_RAID_DMA 0x0021
109 #define PCI_DEVICE_ID_AL_RAID_DMA_VF 0x8021
110 #define PCI_DEVICE_ID_AL_USB 0x0041
113 #define MAC_ADDR(addr) addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]
115 #define AL_ETH_MAC_TABLE_UNICAST_IDX_BASE 0
123 #define AL_ETH_THASH_UDMA_SHIFT 0
124 #define AL_ETH_THASH_UDMA_MASK (0xF << AL_ETH_THASH_UDMA_SHIFT)
127 #define AL_ETH_THASH_Q_MASK (0x3 << AL_ETH_THASH_Q_SHIFT)
130 #define AL_ETH_FSM_ENTRY_IPV4_TCP 0
138 #define AL_ETH_FSM_DATA_OUTER_2_TUPLE 0
145 #define AL_ETH_FSM_DATA_DEFAULT_Q 0
146 #define AL_ETH_FSM_DATA_DEFAULT_UDMA 0
156 #define SFP_I2C_ADDR 0x50
158 #define AL_MASK_GROUP_A_INT 0x7
159 #define AL_MASK_GROUP_B_INT 0xF
160 #define AL_MASK_GROUP_C_INT 0xF
161 #define AL_MASK_GROUP_D_INT 0xFFFFFFFF
163 #define AL_REG_OFFSET_FORWARD_INTR (0x1800000 + 0x1210)
164 #define AL_EN_FORWARD_INTR 0x1FFFF
165 #define AL_DIS_FORWARD_INTR 0
167 #define AL_M2S_MASK_INIT 0x480
168 #define AL_S2M_MASK_INIT 0x1E0
169 #define AL_M2S_S2M_MASK_NOT_INT (0x3f << 25)
232 static int napi = 0;
245 { 0, 0 }
254 DRIVER_MODULE(al, pci, al_driver, 0, 0);
255 DRIVER_MODULE(miibus, al, miibus_driver, 0, 0);
260 if ((al_is_device_supported(dev)) != 0) {
282 err = 0;
284 dev_id = rev_id = 0;
289 if (g_adapters_count == 0) {
291 CTLFLAG_RW, &napi, 0, "Use pseudo-napi mechanism");
341 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
343 if_setflagbits(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | IFF_ALLMULTI, 0);
357 IFCAP_LRO | IFCAP_JUMBO_MTU, 0);
394 if (err != 0)
400 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
401 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10G_LR, 0, NULL);
402 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
409 if (err != 0)
418 callout_init_mtx(&adapter->stats_callout, &adapter->stats_mtx, 0);
419 callout_init_mtx(&adapter->wd_callout, &adapter->wd_mtx, 0);
429 al_media_update, al_media_status, BMSR_DEFCAPMASK, 0,
430 MII_OFFSET_ANY, 0);
431 if (err != 0) {
464 bus_release_resource(dev, SYS_RES_IRQ, 0, adapter->irq_res);
465 bus_release_resource(dev, SYS_RES_MEMORY, 0, adapter->ec_res);
466 bus_release_resource(dev, SYS_RES_MEMORY, 0, adapter->mac_res);
467 bus_release_resource(dev, SYS_RES_MEMORY, 0, adapter->udma_res);
469 return (0);
479 return (0);
488 return (0);
497 return (0);
506 return (0);
560 ret = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
563 if (ret != 0) {
571 if (ret != 0) {
578 size, al_dma_map_addr, baddr, 0);
579 if (ret != 0) {
585 return (0);
601 struct al_eth_fwd_mac_table_entry entry = { { 0 } };
605 memset(entry.mask, 0xff, sizeof(entry.mask));
622 struct al_eth_fwd_mac_table_entry entry = { { 0 } };
624 memset(entry.addr, 0x00, sizeof(entry.addr));
625 memset(entry.mask, 0x00, sizeof(entry.mask));
626 entry.mask[0] |= 1;
627 entry.addr[0] |= 1;
645 struct al_eth_fwd_mac_table_entry entry = { { 0 } };
647 memset(entry.addr, 0xff, sizeof(entry.addr));
648 memset(entry.mask, 0xff, sizeof(entry.mask));
666 struct al_eth_fwd_mac_table_entry entry = { { 0 } };
668 memset(entry.addr, 0x00, sizeof(entry.addr));
669 memset(entry.mask, 0x00, sizeof(entry.mask));
673 entry.udma_mask = (promiscuous) ? 1 : 0;
688 if (udma != 0)
704 for (i = 0; i < AL_ETH_RX_FSM_TABLE_SIZE; i++) {
731 struct al_eth_fwd_mac_table_entry entry = { { 0 } };
746 params->udma_id = 0;
755 if (rc != 0)
764 for (i = 0; i < DMA_MAX_Q; i++) {
767 conf.tx_q_conf[i].tgtid = 0x100; /* for access from PCIE0 */
770 conf.rx_q_conf[i].tgtid = 0x100; /* for access from PCIE0 */
781 struct al_eth_lm_init_params params = {0};
795 if ((adapter->lt_en != 0) && (adapter->an_en != 0))
850 if (rc != 0) {
949 al_eth_mac_addr_read(adapter->ec_base, 0, adapter->mac_addr);
951 return (0);
962 al_eth_mac_addr_read(adapter->ec_base, 0, adapter->mac_addr);
974 al_eth_mac_addr_store(adapter->ec_base, 0, adapter->mac_addr);
984 for (i = 0; i < adapter->num_tx_queues; i++) {
999 for (i = 0; i < adapter->num_rx_queues; i++) {
1021 int rc = 0;
1026 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1027 if (rc == 0)
1028 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1050 return (0);
1078 al_buf->addr = segs[0].ds_addr + AL_IP_ALIGNMENT_OFFSET;
1081 return (0);
1094 for (i = 0; i < num; i++) {
1100 rx_ring, rx_info) < 0)) {
1139 for (i = 0; i < adapter->num_rx_queues; i++)
1155 while (total_done != 0) {
1205 int ehdrlen, ip_hlen = 0;
1206 uint8_t ipproto = 0;
1207 uint32_t offload = 0;
1209 if (mss != 0)
1212 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0)
1215 if ((m->m_pkthdr.csum_flags & CSUM_OFFLOAD) != 0)
1218 if (offload != 0) {
1221 if (mss != 0)
1250 if (mss != 0)
1280 meta->mss_idx_sel = 0; /* check how to select MSS */
1302 if (unlikely(tx_ring->stall) != 0) {
1303 for (a = 0; a < XMIT_QUEUE_TIMEOUT; a++) {
1307 tx_ring->stall = 0;
1370 for (a = 0; a < nsegs; a++) {
1382 if (tx_info->tx_descs == 0)
1412 if (napi != 0) {
1419 if (napi != 0) {
1420 tx_ring->cmpl_is_running = 0;
1441 if ((napi == 0) || (napi && tx_ring->cmpl_is_running == 0))
1462 if ((napi == 0) || (napi && rx_ring->enqueue_is_running == 0))
1503 mbuf->m_pkthdr.csum_flags = 0;
1524 len = hal_pkt->bufs[0].len;
1590 if (napi != 0) {
1599 if (unlikely(descs == 0))
1610 AL_UDMA_CDESC_ERROR)) != 0) {
1612 "flags = 0x%x\n", hal_pkt->flags);
1642 if ((rx_ring->lro_enabled != 0) &&
1643 ((mbuf->m_pkthdr.csum_flags & CSUM_IP_VALID) != 0) &&
1651 if (rx_ring->lro.lro_cnt != 0) {
1652 if (tcp_lro_rx(&rx_ring->lro, mbuf, 0) == 0)
1653 do_if_input = 0;
1675 if (napi != 0) {
1676 rx_ring->enqueue_is_running = 0;
1689 if (napi != 0) {
1705 if (napi != 0) {
1706 tx_ring->enqueue_is_running = 0;
1749 if ((napi == 0) || ((napi != 0) && (tx_ring->enqueue_is_running == 0)))
1784 ((active & AL_ETH_FLOW_CTRL_RX_PAUSE) != 0);
1786 ((active & AL_ETH_FLOW_CTRL_TX_PAUSE) != 0);
1794 for (i = 0; i < AL_ETH_FWD_PRIO_TABLE_NUM; i++)
1795 flow_ctrl_params->prio_q_map[0][i] = 1 << (i >> 1);
1799 return (0);
1820 adapter->link_config.flow_ctrl_active = 0;
1830 if (rc != 0)
1834 if (rc < 0) {
1848 if (rc != 0) {
1859 if (rc != 0) {
1890 return (0);
1919 ®s_base->gen.interrupt_regs.secondary_iofic_ctrl[0];
1920 if (cause_d != 0) {
1936 if ((reg & AL_INT_GROUP_A_GROUP_B_SUM) != 0 ) {
1942 for (qid = 0; qid < adapter->num_rx_queues; qid++) {
1952 if ((reg & AL_INT_GROUP_A_GROUP_C_SUM) != 0) {
1957 for (qid = 0; qid < adapter->num_tx_queues; qid++) {
1958 if ((cause_c & (1 << qid)) != 0) {
1969 return (0);
1978 return (0);
1987 return (0);
2005 adapter->msix_entries[AL_ETH_MGMT_IRQ_IDX].vector = 0;
2008 for (i = 0; i < adapter->num_rx_queues; i++) {
2012 adapter->msix_entries[irq_idx].vector = 0;
2015 for (i = 0; i < adapter->num_tx_queues; i++) {
2020 adapter->msix_entries[irq_idx].vector = 0;
2026 if (rc != 0) {
2040 for (i = 0; i < msix_vecs; i++)
2051 adapter->msix_vecs = 0;
2065 if (rc != 0) {
2072 if (adapter->msix_vecs == 0) {
2079 adapter->irq_tbl[AL_ETH_MGMT_IRQ_IDX].vector = 0;
2085 return (0);
2098 return (0);
2109 for (i = 0; i < adapter->num_rx_queues; i++) {
2121 for (i = 0; i < adapter->num_tx_queues; i++) {
2133 return (0);
2142 for (i = 0; i < adapter->irq_vecs; i++) {
2144 if (irq->requested != 0) {
2149 if (rc != 0)
2153 irq->requested = 0;
2171 for (i = 0; i < adapter->irq_vecs; i++) {
2180 if (rc != 0)
2189 adapter->msix_vecs = 0;
2199 int rc = 0, i, v;
2201 if ((adapter->flags & AL_ETH_FLAG_MSIX_ENABLED) != 0)
2206 for (i = 0; i < adapter->irq_vecs; i++) {
2209 if (irq->requested != 0)
2223 NULL, irq->data, &irq->cookie)) != 0) {
2235 while (v-- >= 0) {
2239 if (bti != 0) {
2244 irq->requested = 0;
2251 while (v-- >= 0) {
2258 if (brr != 0)
2273 * Return 0 on success, negative on failure
2285 return (0);
2297 if (ret != 0) {
2314 TASK_INIT(&tx_ring->enqueue_task, 0, al_eth_start_xmit, tx_ring);
2319 TASK_INIT(&tx_ring->cmpl_task, 0, al_eth_tx_cmpl_work, tx_ring);
2327 1, 0, /* alignment, bounds */
2334 0, /* flags */
2339 if (ret != 0) {
2345 for (size = 0; size < tx_ring->sw_count; size++) {
2346 ret = bus_dmamap_create(tx_ring->dma_buf_tag, 0,
2348 if (ret != 0) {
2359 tx_ring->next_to_use = 0;
2360 tx_ring->next_to_clean = 0;
2362 return (0);
2396 for (size = 0; size < tx_ring->sw_count; size++) {
2433 for (i = 0; i < adapter->num_tx_queues; i++)
2443 * Returns 0 on success, negative on failure
2468 if ((q_params->desc_base == NULL) || (ret != 0))
2479 if ((q_params->cdesc_base == NULL) || (ret != 0))
2483 NET_TASK_INIT(&rx_ring->enqueue_task, 0, al_eth_rx_recv_work, rx_ring);
2491 1, 0, /* alignment, bounds */
2498 0, /* flags */
2503 if (ret != 0) {
2508 for (size = 0; size < rx_ring->sw_count; size++) {
2509 ret = bus_dmamap_create(rx_ring->dma_buf_tag, 0,
2511 if (ret != 0) {
2518 memset(q_params->cdesc_base, 0, rx_ring->cdescs_size);
2521 if ((if_getcapenable(adapter->netdev) & IFCAP_LRO) != 0) {
2523 if (err != 0) {
2534 rx_ring->next_to_clean = 0;
2535 rx_ring->next_to_use = 0;
2537 return (0);
2562 for (size = 0; size < rx_ring->sw_count; size++) {
2591 q_params->cdesc_phy_base = 0;
2608 for (i = 0; i < adapter->num_rx_queues; i++)
2609 if (adapter->rx_ring[i].q_params.desc_base != 0)
2617 * Return 0 on success, negative on failure
2622 int i, rc = 0;
2624 for (i = 0; i < adapter->num_rx_queues; i++) {
2626 if (rc == 0)
2632 return (0);
2645 * Return 0 on success, negative on failure
2650 int i, rc = 0;
2652 for (i = 0; i < adapter->num_tx_queues; i++) {
2654 if (rc == 0)
2662 return (0);
2739 if (adapter->msix_vecs == 0)
2771 adapter->tx_usecs = 0;
2772 adapter->rx_usecs = 0;
2774 return (0);
2796 if (adapter->up == 0)
2828 return (0);
2854 if (mac[3] != 0 && mac[4] != 0 && mac[5] != 1)
2857 return (0);
2890 if ((if_getflags(ifp) & IFF_PROMISC) != 0) {
2893 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) {
2898 if (mc == 0) {
2906 if (uc != 0) {
2938 for (i = 0; i < AL_ETH_FWD_PBITS_TABLE_NUM; i++)
2942 for (i = 0; i < AL_ETH_FWD_PRIO_TABLE_NUM; i++)
2963 for (i = 0; i < sizeof(adapter->toeplitz_hash_key); i++)
2966 for (i = 0; i < AL_ETH_RX_HASH_KEY_NUM; i++)
2970 for (i = 0; i < AL_ETH_RX_RSS_TABLE_SIZE; i++) {
2973 al_eth_set_thash_table_entry(adapter, i, 0,
3022 al_eth_tso_mss_config(&adapter->hal_adapter, 0, new_mtu - 100);
3024 return (0);
3037 return (0);
3044 int rc = 0;
3054 if (rc < 0) {
3067 for (i = 0; i < adapter->num_tx_queues; i++)
3070 for (i = 0; i < adapter->num_rx_queues; i++)
3073 return (0);
3108 if ((if_getflags(ifp) & IFF_UP) != 0)
3111 return (0);
3122 ifmr->ifm_status = 0;
3162 return (0);
3164 if ((adapter->flags & AL_ETH_FLAG_RESET_REQUESTED) != 0) {
3169 if_sethwassist(ifp, 0);
3170 if ((if_getcapenable(ifp) & IFCAP_TSO) != 0)
3171 if_sethwassistbits(ifp, CSUM_TSO, 0);
3172 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
3173 if_sethwassistbits(ifp, (CSUM_TCP | CSUM_UDP), 0);
3174 if ((if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) != 0)
3175 if_sethwassistbits(ifp, (CSUM_TCP_IPV6 | CSUM_UDP_IPV6), 0);
3180 if (rc != 0)
3184 if (rc != 0) {
3192 if (rc != 0)
3197 if (rc != 0)
3201 if (rc != 0)
3245 return (0);
3278 int error = 0;
3284 if (error != 0) {
3290 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3296 if ((if_getflags(ifp) & IFF_UP) != 0) {
3297 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
3299 (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3306 if (error == 0)
3307 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
3310 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
3312 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3321 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
3326 if ((if_getcapenable(ifp) & IFCAP_POLLING) == 0)
3343 reinit = 0;
3346 if ((mask & IFCAP_POLLING) != 0) {
3347 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
3348 if (error != 0)
3350 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
3354 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
3358 if ((mask & IFCAP_HWCSUM) != 0) {
3363 if ((mask & IFCAP_HWCSUM_IPV6) != 0) {
3367 if ((mask & IFCAP_TSO) != 0) {
3371 if ((mask & IFCAP_LRO) != 0) {
3374 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
3378 if ((mask & IFCAP_VLAN_HWFILTER) != 0) {
3382 if ((mask & IFCAP_VLAN_HWTSO) != 0) {
3386 if ((reinit != 0) &&
3387 ((if_getdrvflags(ifp) & IFF_DRV_RUNNING)) != 0)
3423 uint16_t value = 0;
3427 while (timeout > 0) {
3431 if (rc == 0)
3441 if (rc != 0)
3454 while (timeout > 0) {
3458 if (rc == 0)
3459 return (0);
3468 if (rc != 0)
3482 "al_miibus_statchg: active = 0x%x status = 0x%x\n",
3485 if (adapter->up == 0)
3488 if ((adapter->mii->mii_media_status & IFM_AVALID) != 0) {
3503 uint8_t duplex = 0;
3504 uint8_t speed = 0;
3509 if ((if_getflags(adapter->netdev) & IFF_UP) == 0)
3518 if ((adapter->mii->mii_media_active & IFM_FDX) != 0)
3524 al_eth_mac_link_config(&adapter->hal_adapter, 0, 1,
3530 al_eth_mac_link_config(&adapter->hal_adapter, 0, 1,
3536 al_eth_mac_link_config(&adapter->hal_adapter, 0, 1,
3541 device_printf(adapter->dev, "ERROR: unknown MII media active 0x%08x\n",