Lines Matching +full:cmd +full:- +full:timeout +full:- +full:ms
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
108 return ch->disablephy ? ATA_SC_DET_DISABLE : val;
116 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
118 if (ctlr->ccc) {
119 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
120 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
121 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
124 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
128 "CCC with %dms/4cmd enabled on vector %d\n",
129 ctlr->ccc, ctlr->cccv);
133 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
134 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
143 int timeout;
146 if ((ATA_INL(ctlr->r_mem, AHCI_VS) >= 0x00010200) &&
147 (ATA_INL(ctlr->r_mem, AHCI_CAP2) & AHCI_CAP2_BOH) &&
148 ((v = ATA_INL(ctlr->r_mem, AHCI_BOHC)) & AHCI_BOHC_OOS) == 0) {
150 ATA_OUTL(ctlr->r_mem, AHCI_BOHC, v | AHCI_BOHC_OOS);
153 for (timeout = 0; timeout < 80; timeout++) {
155 v = ATA_INL(ctlr->r_mem, AHCI_BOHC);
164 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
166 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
167 for (timeout = 1000; timeout > 0; timeout--) {
169 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
172 if (timeout == 0) {
177 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
179 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) {
182 * This is write to a read-only register to restore its state.
183 * On fully standard-compliant hardware this is not needed and
187 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps);
201 ctlr->dev = dev;
202 ctlr->ccc = 0;
204 device_get_unit(dev), "ccc", &ctlr->ccc);
205 mtx_init(&ctlr->ch_mtx, "AHCI channels lock", NULL, MTX_DEF);
208 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
209 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
210 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
211 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
212 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
216 if ((error = rman_manage_region(&ctlr->sc_iomem,
217 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
219 rman_fini(&ctlr->sc_iomem);
223 version = ATA_INL(ctlr->r_mem, AHCI_VS);
224 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
226 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
227 if (ctlr->caps & AHCI_CAP_EMS)
228 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
230 if (ctlr->quirks & AHCI_Q_FORCE_PI) {
237 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1;
238 int nmask = (1 << nports) - 1;
240 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask);
245 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
248 if ((ctlr->quirks & AHCI_Q_ALTSIG) &&
249 (ctlr->caps & AHCI_CAP_SPM) == 0)
250 ctlr->quirks |= AHCI_Q_NOBSYRES;
252 if (ctlr->quirks & AHCI_Q_1CH) {
253 ctlr->caps &= ~AHCI_CAP_NPMASK;
254 ctlr->ichannels &= 0x01;
256 if (ctlr->quirks & AHCI_Q_2CH) {
257 ctlr->caps &= ~AHCI_CAP_NPMASK;
258 ctlr->caps |= 1;
259 ctlr->ichannels &= 0x03;
261 if (ctlr->quirks & AHCI_Q_4CH) {
262 ctlr->caps &= ~AHCI_CAP_NPMASK;
263 ctlr->caps |= 3;
264 ctlr->ichannels &= 0x0f;
266 ctlr->channels = MAX(flsl(ctlr->ichannels),
267 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
268 if (ctlr->quirks & AHCI_Q_NOPMP)
269 ctlr->caps &= ~AHCI_CAP_SPM;
270 if (ctlr->quirks & AHCI_Q_NONCQ)
271 ctlr->caps &= ~AHCI_CAP_SNCQ;
272 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
273 ctlr->ccc = 0;
274 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
276 /* Create controller-wide DMA tag. */
278 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
281 ctlr->dma_coherent ? BUS_DMA_COHERENT : 0, NULL, NULL,
282 &ctlr->dma_tag)) {
284 rman_fini(&ctlr->sc_iomem);
292 bus_dma_tag_destroy(ctlr->dma_tag);
294 rman_fini(&ctlr->sc_iomem);
299 for (u = ctlr->ichannels; u != 0; u >>= 1)
301 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
303 "direct", &ctlr->direct);
305 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
310 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
313 (ctlr->caps & AHCI_CAP_SPM) ?
315 (ctlr->caps & AHCI_CAP_FBSS) ?
317 if (ctlr->quirks != 0) {
318 device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
323 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
324 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
325 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
326 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
327 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
328 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
329 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
330 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
334 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
335 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
336 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
337 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
338 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
339 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
340 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
341 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
342 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
343 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
344 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
348 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
349 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
350 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
351 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
352 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
353 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
356 for (unit = 0; unit < ctlr->channels; unit++) {
363 if ((ctlr->ichannels & (1 << unit)) == 0)
367 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
376 int em = (ctlr->caps & AHCI_CAP_EMS) != 0;
402 for (i = 0; i < ctlr->numirqs; i++) {
403 if (ctlr->irqs[i].r_irq) {
404 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
405 ctlr->irqs[i].handle);
407 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
410 bus_dma_tag_destroy(ctlr->dma_tag);
412 rman_fini(&ctlr->sc_iomem);
414 mtx_destroy(&ctlr->ch_mtx);
424 if (ctlr->r_mem)
425 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
426 if (ctlr->r_msix_table)
428 ctlr->r_msix_tab_rid, ctlr->r_msix_table);
429 if (ctlr->r_msix_pba)
431 ctlr->r_msix_pba_rid, ctlr->r_msix_pba);
433 ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL;
443 if (ctlr->numirqs > 1 &&
444 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
446 ctlr->numirqs = 1;
450 if (ctlr->numirqs > AHCI_MAX_IRQS) {
452 ctlr->numirqs, AHCI_MAX_IRQS);
453 ctlr->numirqs = AHCI_MAX_IRQS;
457 for (i = 0; i < ctlr->numirqs; i++) {
458 ctlr->irqs[i].ctlr = ctlr;
459 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
460 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi)
461 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
462 else if (ctlr->numirqs == 1 || i >= ctlr->channels ||
463 (ctlr->ccc && i == ctlr->cccv))
464 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
465 else if (ctlr->channels > ctlr->numirqs &&
466 i == ctlr->numirqs - 1)
467 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
469 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
470 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
471 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
475 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
476 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
477 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
479 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
484 if (ctlr->numirqs > 1) {
485 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
486 ctlr->irqs[i].handle,
487 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
501 struct ahci_controller *ctlr = irq->ctlr;
506 if (irq->mode == AHCI_IRQ_MODE_ALL) {
508 if (ctlr->ccc)
509 is = ctlr->ichannels;
511 is = ATA_INL(ctlr->r_mem, AHCI_IS);
513 unit = irq->r_irq_rid - 1;
514 is = ATA_INL(ctlr->r_mem, AHCI_IS);
518 if (ctlr->ccc)
519 ise = 1 << ctlr->cccv;
521 if (ctlr->quirks & AHCI_Q_EDGEIS)
524 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
525 for (; unit < ctlr->channels; unit++) {
527 (arg = ctlr->interrupt[unit].argument)) {
528 ctlr->interrupt[unit].function(arg);
531 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
532 if ((arg = ctlr->interrupt[unit].argument)) {
533 ctlr->interrupt[unit].function(arg);
538 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
539 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
540 ATA_RBL(ctlr->r_mem, AHCI_IS);
550 struct ahci_controller *ctlr = irq->ctlr;
554 unit = irq->r_irq_rid - 1;
555 if ((arg = ctlr->interrupt[unit].argument))
556 ctlr->interrupt[unit].function(arg);
558 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
559 ATA_RBL(ctlr->r_mem, AHCI_IS);
566 struct ahci_controller *ctlr = irq->ctlr;
570 unit = irq->r_irq_rid - 1;
572 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
573 if ((arg = ctlr->interrupt[unit].argument))
574 ctlr->interrupt[unit].function(arg);
575 ATA_RBL(ctlr->r_mem, AHCI_IS);
592 unit -= ctlr->channels;
602 offset = ctlr->remap_offset + unit * ctlr->remap_size;
603 size = ctlr->remap_size;
607 } else if ((ctlr->caps & AHCI_CAP_EMS) == 0) {
613 offset = (ctlr->emloc & 0xffff0000) >> 14;
614 size = (ctlr->emloc & 0x0000ffff) << 2;
616 if (*rid == 2 && (ctlr->capsem &
623 st = rman_get_start(ctlr->r_mem);
624 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
625 st + offset + size - 1, size, RF_ACTIVE, child);
629 bsh = rman_get_bushandle(ctlr->r_mem);
630 bst = rman_get_bustag(ctlr->r_mem);
638 res = ctlr->irqs[0].r_irq;
672 ctlr->interrupt[unit].function = function;
673 ctlr->interrupt[unit].argument = argument;
684 ctlr->interrupt[unit].function = NULL;
685 ctlr->interrupt[unit].argument = NULL;
719 return (ctlr->dma_tag);
727 mtx_lock(&ctlr->ch_mtx);
728 ctlr->ch[ch->unit] = ch;
729 mtx_unlock(&ctlr->ch_mtx);
737 mtx_lock(&ctlr->ch_mtx);
738 mtx_lock(&ch->mtx);
739 ctlr->ch[ch->unit] = NULL;
740 mtx_unlock(&ch->mtx);
741 mtx_unlock(&ctlr->ch_mtx);
751 mtx_lock(&ctlr->ch_mtx);
752 ch = ctlr->ch[n];
754 mtx_lock(&ch->mtx);
755 mtx_unlock(&ctlr->ch_mtx);
763 mtx_unlock(&ch->mtx);
781 value = ch->disablephy;
783 if (error != 0 || req->newptr == NULL || (value != 0 && value != 1))
786 mtx_lock(&ch->mtx);
787 ch->disablephy = value;
789 ahci_ch_deinit(ch->dev);
791 ahci_ch_init(ch->dev);
794 mtx_unlock(&ch->mtx);
810 ch->dev = dev;
811 ch->unit = (intptr_t)device_get_ivars(dev);
812 ch->caps = ctlr->caps;
813 ch->caps2 = ctlr->caps2;
814 ch->start = ctlr->ch_start;
815 ch->quirks = ctlr->quirks;
816 ch->vendorid = ctlr->vendorid;
817 ch->deviceid = ctlr->deviceid;
818 ch->subvendorid = ctlr->subvendorid;
819 ch->subdeviceid = ctlr->subdeviceid;
820 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
821 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
822 ch->pm_level = 0;
824 device_get_unit(dev), "pm_level", &ch->pm_level);
825 STAILQ_INIT(&ch->doneq);
826 if (ch->pm_level > 3)
827 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
828 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
830 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
832 if (ch->quirks & AHCI_Q_SATA2)
837 ch->user[i].revision = sata_rev;
838 ch->user[i].mode = 0;
839 ch->user[i].bytecount = 8192;
840 ch->user[i].tags = ch->numslots;
841 ch->user[i].caps = 0;
842 ch->curr[i] = ch->user[i];
843 if (ch->pm_level) {
844 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
848 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
852 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
855 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
856 version = ATA_INL(ctlr->r_mem, AHCI_VS);
857 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
858 ch->chcaps |= AHCI_P_CMD_FBSCP;
859 if (ch->caps2 & AHCI_CAP2_SDS)
860 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
863 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
864 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
865 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
866 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
867 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"",
868 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":"");
872 mtx_lock(&ch->mtx);
875 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
881 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
882 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
883 ch, &ch->ih))) {
889 devq = cam_simq_alloc(ch->numslots);
896 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
897 device_get_unit(dev), (struct mtx *)&ch->mtx,
898 (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots),
899 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
901 if (ch->sim == NULL) {
907 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
912 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
918 if (ch->pm_level > 3) {
919 callout_reset(&ch->pm_timer,
920 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
923 mtx_unlock(&ch->mtx);
933 xpt_bus_deregister(cam_sim_path(ch->sim));
935 cam_sim_free(ch->sim, /*free_devq*/TRUE);
937 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
939 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
940 mtx_unlock(&ch->mtx);
941 mtx_destroy(&ch->mtx);
951 mtx_lock(&ch->mtx);
952 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
954 if (ch->resetting) {
955 ch->resetting = 0;
956 xpt_release_simq(ch->sim, TRUE);
958 xpt_free_path(ch->path);
959 xpt_bus_deregister(cam_sim_path(ch->sim));
960 cam_sim_free(ch->sim, /*free_devq*/TRUE);
961 mtx_unlock(&ch->mtx);
963 if (ch->pm_level > 3)
964 callout_drain(&ch->pm_timer);
965 callout_drain(&ch->reset_timer);
966 bus_teardown_intr(dev, ch->r_irq, ch->ih);
967 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
973 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
974 mtx_destroy(&ch->mtx);
985 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
987 work = ch->dma.work_bus + AHCI_CL_OFFSET;
988 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
989 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
990 work = ch->dma.rfis_bus;
991 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
992 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
994 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
996 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
997 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
1009 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1013 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
1015 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
1017 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
1020 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
1029 mtx_lock(&ch->mtx);
1030 xpt_freeze_simq(ch->sim, 1);
1032 if (ch->resetting) {
1033 ch->resetting = 0;
1034 callout_stop(&ch->reset_timer);
1035 xpt_release_simq(ch->sim, TRUE);
1037 while (ch->oslots)
1038 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
1040 mtx_unlock(&ch->mtx);
1049 mtx_lock(&ch->mtx);
1052 xpt_release_simq(ch->sim, TRUE);
1053 mtx_unlock(&ch->mtx);
1089 0, NULL, NULL, &ch->dma.work_tag);
1092 error = bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
1093 BUS_DMA_ZERO, &ch->dma.work_map);
1096 error = bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1099 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1102 ch->dma.work_bus = dcba.maddr;
1104 if (ch->chcaps & AHCI_P_CMD_FBSCP)
1111 0, NULL, NULL, &ch->dma.rfis_tag);
1114 error = bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1115 &ch->dma.rfis_map);
1118 error = bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1121 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1124 ch->dma.rfis_bus = dcba.maddr;
1130 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag);
1136 device_printf(dev, "WARNING - DMA initialization failed, error %d\n",
1146 if (!(dcba->error = error))
1147 dcba->maddr = segs[0].ds_addr;
1155 if (ch->dma.data_tag) {
1156 bus_dma_tag_destroy(ch->dma.data_tag);
1157 ch->dma.data_tag = NULL;
1159 if (ch->dma.rfis_bus) {
1160 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1161 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1162 ch->dma.rfis_bus = 0;
1163 ch->dma.rfis = NULL;
1165 if (ch->dma.work_bus) {
1166 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1167 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1168 ch->dma.work_bus = 0;
1169 ch->dma.work = NULL;
1171 if (ch->dma.work_tag) {
1172 bus_dma_tag_destroy(ch->dma.work_tag);
1173 ch->dma.work_tag = NULL;
1184 bzero(ch->slot, sizeof(ch->slot));
1185 for (i = 0; i < ch->numslots; i++) {
1186 struct ahci_slot *slot = &ch->slot[i];
1188 slot->ch = ch;
1189 slot->slot = i;
1190 slot->state = AHCI_SLOT_EMPTY;
1191 slot->ct_offset = AHCI_CT_OFFSET + AHCI_CT_SIZE * i;
1192 slot->ccb = NULL;
1193 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1195 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1196 device_printf(ch->dev, "FAILURE - create data_map\n");
1207 for (i = 0; i < ch->numslots; i++) {
1208 struct ahci_slot *slot = &ch->slot[i];
1210 callout_drain(&slot->timeout);
1211 if (slot->dma.data_map) {
1212 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1213 slot->dma.data_map = NULL;
1222 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1223 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1224 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1229 device_printf(ch->dev, "CONNECT requested\n");
1231 device_printf(ch->dev, "DISCONNECT requested\n");
1236 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1237 cam_sim_path(ch->sim),
1255 if (ch->pm_level == 0)
1258 status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1263 dev = ch->dev;
1272 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1286 if (ch->caps & AHCI_CAP_SSNTF)
1287 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1289 device_printf(ch->dev, "SNTF 0x%04x\n", status);
1294 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1305 mtx_assert(&ch->mtx, MA_OWNED);
1306 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 ||
1307 ch->batch == 0) {
1312 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe);
1322 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1324 mtx_lock(&ch->mtx);
1326 mtx_unlock(&ch->mtx);
1338 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1340 mtx_lock(&ch->mtx);
1341 ch->batch = 1;
1343 ch->batch = 0;
1348 STAILQ_CONCAT(&tmp_doneq, &ch->doneq);
1349 mtx_unlock(&ch->mtx);
1362 if (ch->numrslots != 0)
1364 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1365 if (ch->pm_level == 4)
1369 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1380 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1382 if (ch->numtslots != 0)
1383 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1386 if (ch->numrslots != ch->numtslots)
1387 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1390 (ch->pm_present || ch->curr[0].atapi != 0)) {
1391 if (ch->caps & AHCI_CAP_SSNTF)
1392 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1393 else if (ch->fbs_enabled) {
1394 u_int8_t *fis = ch->dma.rfis + 0x58;
1404 u_int8_t *fis = ch->dma.rfis + 0x58;
1413 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1415 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1425 if (ch->quirks & AHCI_Q_NOCCS) {
1430 cstatus |= ch->rslots;
1433 ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1;
1435 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) &
1439 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1440 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1441 port = -1;
1442 if (ch->fbs_enabled) {
1443 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1449 if (ch->numrslotspd[i] == 0)
1451 if (port == -1)
1454 port = -2;
1460 err = ch->rslots & cstatus;
1464 port = -1;
1467 ok = ch->rslots & ~cstatus;
1468 for (i = 0; i < ch->numslots; i++) {
1470 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1474 if (ch->frozen) {
1475 union ccb *fccb = ch->frozen;
1476 ch->frozen = NULL;
1477 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1478 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1479 xpt_freeze_devq(fccb->ccb_h.path, 1);
1480 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1484 for (i = 0; i < ch->numslots; i++) {
1489 ch->slot[i].ccb->ccb_h.target_id != port)
1492 if (port != -2) {
1494 if (ch->numtslotspd[
1495 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1507 ch->fatalerr = 1;
1510 if (ch->numtslots == 0 && i != ccs && port != -2)
1516 ahci_end_transaction(&ch->slot[i], et);
1522 if (ch->rslots != 0 && !ch->recoverycmd)
1523 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1534 int t = ccb->ccb_h.target_id;
1536 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1537 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1539 if (((~ch->oslots) & (0xffffffff >> (32 -
1540 ch->curr[t].tags))) == 0)
1543 if (ch->fbs_enabled) {
1545 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1549 if (ch->numrslots != 0 && ch->numtslots == 0)
1552 if (ch->numtslots != 0 &&
1553 ch->taggedtarget != ccb->ccb_h.target_id)
1558 if (ch->fbs_enabled) {
1560 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1564 if (ch->numrslots != 0 && ch->numtslots != 0)
1568 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1569 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1571 if (ch->numrslots != 0)
1575 if (ch->aslots != 0)
1588 tags = ch->numslots;
1589 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1590 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1591 tags = ch->curr[ccb->ccb_h.target_id].tags;
1592 if (ch->lastslot + 1 < tags)
1593 tag = ffs(~(ch->oslots >> (ch->lastslot + 1)));
1596 if (tag == 0 || tag + ch->lastslot >= tags)
1597 tag = ffs(~ch->oslots) - 1;
1599 tag += ch->lastslot;
1600 ch->lastslot = tag;
1602 slot = &ch->slot[tag];
1603 slot->ccb = ccb;
1605 if (ch->numrslots == 0 && ch->pm_level > 3)
1606 callout_stop(&ch->pm_timer);
1608 ch->oslots |= (1 << tag);
1609 ch->numrslots++;
1610 ch->numrslotspd[ccb->ccb_h.target_id]++;
1611 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1612 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1613 ch->numtslots++;
1614 ch->numtslotspd[ccb->ccb_h.target_id]++;
1615 ch->taggedtarget = ccb->ccb_h.target_id;
1617 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1618 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1619 ch->aslots |= (1 << tag);
1620 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1621 slot->state = AHCI_SLOT_LOADING;
1622 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1625 slot->dma.nsegs = 0;
1635 struct ahci_channel *ch = slot->ch;
1641 device_printf(ch->dev, "DMA load error\n");
1647 ctp = (struct ahci_cmd_tab *)(ch->dma.work + slot->ct_offset);
1649 prd = &ctp->prd_tab[0];
1652 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1654 slot->dma.nsegs = nsegs;
1655 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1656 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1665 struct ahci_channel *ch = slot->ch;
1668 union ccb *ccb = slot->ccb;
1669 int port = ccb->ccb_h.target_id & 0x0f;
1671 uint8_t *fis = ch->dma.rfis + 0x40;
1676 ctp = (struct ahci_cmd_tab *)(ch->dma.work + slot->ct_offset);
1678 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) {
1679 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1685 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1687 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1688 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1692 clp->prd_length = htole16(slot->dma.nsegs);
1694 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1695 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1696 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1711 clp->bytecount = 0;
1712 clp->cmd_flags = htole16(cmd_flags);
1713 clp->cmd_table_phys = htole64(ch->dma.work_bus + slot->ct_offset);
1714 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1716 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1719 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1720 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1721 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1724 if (ch->fbs_enabled) {
1725 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1729 slot->state = AHCI_SLOT_RUNNING;
1730 ch->rslots |= (1 << slot->slot);
1731 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1733 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1734 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1735 int count, timeout = ccb->ccb_h.timeout * 100;
1738 for (count = 0; count < timeout; count++) {
1740 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1742 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1745 device_printf(ch->dev,
1747 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1753 if (ccb->ccb_h.target_id == 15 &&
1754 (ch->quirks & AHCI_Q_ATI_PMP_BUG) &&
1755 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1764 * to 50ms after soft reset.
1766 if (ch->quirks & AHCI_Q_MRVL_SR_DEL)
1770 * Marvell HBAs with non-RAID firmware do not wait for
1776 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 &&
1777 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 &&
1779 for ( ; count < timeout; count++) {
1780 bus_dmamap_sync(ch->dma.rfis_tag,
1781 ch->dma.rfis_map, BUS_DMASYNC_POSTREAD);
1783 bus_dmamap_sync(ch->dma.rfis_tag,
1784 ch->dma.rfis_map, BUS_DMASYNC_PREREAD);
1791 if (timeout && (count >= timeout)) {
1792 device_printf(ch->dev, "Poll timeout on slot %d port %d\n",
1793 slot->slot, port);
1794 device_printf(ch->dev, "is %08x cs %08x ss %08x "
1795 "rs %08x tfd %02x serr %08x cmd %08x\n",
1796 ATA_INL(ch->r_mem, AHCI_P_IS),
1797 ATA_INL(ch->r_mem, AHCI_P_CI),
1798 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1799 ATA_INL(ch->r_mem, AHCI_P_TFD),
1800 ATA_INL(ch->r_mem, AHCI_P_SERR),
1801 ATA_INL(ch->r_mem, AHCI_P_CMD));
1807 ch->eslots |= (1 << slot->slot);
1811 /* Start command execution timeout */
1812 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2,
1823 mtx_assert(&ch->mtx, MA_OWNED);
1825 for (i = 0; i < ch->numslots; i++) {
1827 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1829 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1839 mtx_assert(&ch->mtx, MA_OWNED);
1840 for (i = 0; i < ch->numslots; i++) {
1841 struct ahci_slot *slot = &ch->slot[i];
1844 if (slot->state < AHCI_SLOT_RUNNING)
1846 if ((ch->toslots & (1 << i)) == 0)
1848 callout_reset_sbt(&slot->timeout,
1849 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1859 struct ahci_channel *ch = slot->ch;
1860 device_t dev = ch->dev;
1865 /* Check for stale timeout. */
1866 if (slot->state < AHCI_SLOT_RUNNING)
1870 if (slot->state < AHCI_SLOT_EXECUTING) {
1872 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1873 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1875 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1876 ch->fbs_enabled || ch->wrongccs)
1877 slot->state = AHCI_SLOT_EXECUTING;
1878 else if ((ch->rslots & (1 << ccs)) == 0) {
1879 ch->wrongccs = 1;
1880 slot->state = AHCI_SLOT_EXECUTING;
1883 callout_reset_sbt(&slot->timeout,
1884 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1889 device_printf(dev, "Timeout on slot %d port %d\n",
1890 slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
1892 "serr %08x cmd %08x\n",
1893 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1894 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1895 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
1896 ATA_INL(ch->r_mem, AHCI_P_CMD));
1899 if (ch->frozen) {
1900 union ccb *fccb = ch->frozen;
1901 ch->frozen = NULL;
1902 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1903 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1904 xpt_freeze_devq(fccb->ccb_h.path, 1);
1905 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1909 if (!ch->fbs_enabled && !ch->wrongccs) {
1910 /* Without FBS we know real timeout source. */
1911 ch->fatalerr = 1;
1912 /* Handle command with timeout. */
1913 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1915 for (i = 0; i < ch->numslots; i++) {
1917 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1919 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1922 /* With FBS we wait for other commands timeout and pray. */
1923 if (ch->toslots == 0)
1924 xpt_freeze_simq(ch->sim, 1);
1925 ch->toslots |= (1 << slot->slot);
1926 if ((ch->rslots & ~ch->toslots) == 0)
1930 ch->rslots & ~ch->toslots);
1938 struct ahci_channel *ch = slot->ch;
1939 union ccb *ccb = slot->ccb;
1944 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1947 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1952 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1953 struct ata_res *res = &ccb->ataio.res;
1956 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1957 u_int8_t *fis = ch->dma.rfis + 0x40;
1959 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1961 if (ch->fbs_enabled) {
1962 fis += ccb->ccb_h.target_id * 256;
1963 res->status = fis[2];
1964 res->error = fis[3];
1966 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1968 res->status = tfd;
1969 res->error = tfd >> 8;
1971 res->lba_low = fis[4];
1972 res->lba_mid = fis[5];
1973 res->lba_high = fis[6];
1974 res->device = fis[7];
1975 res->lba_low_exp = fis[8];
1976 res->lba_mid_exp = fis[9];
1977 res->lba_high_exp = fis[10];
1978 res->sector_count = fis[12];
1979 res->sector_count_exp = fis[13];
1985 if ((ch->quirks & AHCI_Q_ALTSIG) &&
1986 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1987 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1988 sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
1989 res->lba_high = sig >> 24;
1990 res->lba_mid = sig >> 16;
1991 res->lba_low = sig >> 8;
1992 res->sector_count = sig;
1996 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
1997 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1998 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
1999 ccb->ataio.resid =
2000 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
2003 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2004 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2005 ccb->csio.resid =
2006 ccb->csio.dxfer_len - le32toh(clp->bytecount);
2009 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2010 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
2011 (ccb->ccb_h.flags & CAM_DIR_IN) ?
2013 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
2016 ch->eslots |= (1 << slot->slot);
2018 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
2019 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2020 xpt_freeze_devq(ccb->ccb_h.path, 1);
2021 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2024 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2027 ccb->ccb_h.status |= CAM_REQ_CMP;
2028 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
2029 ccb->csio.scsi_status = SCSI_STATUS_OK;
2032 ch->fatalerr = 1;
2033 ccb->ccb_h.status |= CAM_REQ_INVALID;
2036 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
2040 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2041 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2042 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2044 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2048 ch->fatalerr = 1;
2049 if (!ch->recoverycmd) {
2050 xpt_freeze_simq(ch->sim, 1);
2051 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2052 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2054 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
2057 if (!ch->recoverycmd) {
2058 xpt_freeze_simq(ch->sim, 1);
2059 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2060 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2062 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2065 ch->fatalerr = 1;
2066 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
2069 ch->oslots &= ~(1 << slot->slot);
2070 ch->rslots &= ~(1 << slot->slot);
2071 ch->aslots &= ~(1 << slot->slot);
2072 slot->state = AHCI_SLOT_EMPTY;
2073 slot->ccb = NULL;
2075 ch->numrslots--;
2076 ch->numrslotspd[ccb->ccb_h.target_id]--;
2077 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2078 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
2079 ch->numtslots--;
2080 ch->numtslotspd[ccb->ccb_h.target_id]--;
2082 /* Cancel timeout state if request completed normally. */
2084 lastto = (ch->toslots == (1 << slot->slot));
2085 ch->toslots &= ~(1 << slot->slot);
2087 xpt_release_simq(ch->sim, TRUE);
2091 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2092 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2093 (ccb->ataio.cmd.control & ATA_A_RESET) &&
2095 ccb->ataio.cmd.control &= ~ATA_A_RESET;
2099 /* If it was our READ LOG command - process it. */
2100 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
2102 /* If it was our REQUEST SENSE command - process it. */
2103 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
2107 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
2108 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
2109 ch->hold[slot->slot] = ccb;
2110 ch->numhslots++;
2114 if (ch->rslots == 0) {
2115 /* if there was fatal error - reset port. */
2116 if (ch->toslots != 0 || ch->fatalerr) {
2120 if (ch->eslots != 0) {
2126 if (!ch->recoverycmd && ch->numhslots)
2129 /* If all the rest of commands are in timeout - give them chance. */
2130 } else if ((ch->rslots & ~ch->toslots) == 0 &&
2134 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) {
2135 union ccb *fccb = ch->frozen;
2136 ch->frozen = NULL;
2138 xpt_release_simq(ch->sim, TRUE);
2141 if (ch->numrslots == 0 && ch->pm_level > 3 &&
2142 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
2143 callout_schedule(&ch->pm_timer,
2144 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
2157 for (i = 0; i < ch->numslots; i++) {
2158 if (ch->hold[i])
2163 device_printf(ch->dev, "Unable to allocate recovery command\n");
2165 /* We can't do anything -- complete held commands. */
2166 for (i = 0; i < ch->numslots; i++) {
2167 if (ch->hold[i] == NULL)
2169 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2170 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2171 ahci_done(ch, ch->hold[i]);
2172 ch->hold[i] = NULL;
2173 ch->numhslots--;
2178 xpt_setup_ccb(&ccb->ccb_h, ch->hold[i]->ccb_h.path,
2179 ch->hold[i]->ccb_h.pinfo.priority);
2180 if (ch->hold[i]->ccb_h.func_code == XPT_ATA_IO) {
2182 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2183 ccb->ccb_h.func_code = XPT_ATA_IO;
2184 ccb->ccb_h.flags = CAM_DIR_IN;
2185 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2186 ataio = &ccb->ataio;
2187 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2188 if (ataio->data_ptr == NULL) {
2190 device_printf(ch->dev,
2194 ataio->dxfer_len = 512;
2195 bzero(&ataio->cmd, sizeof(ataio->cmd));
2196 ataio->cmd.flags = CAM_ATAIO_48BIT;
2197 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2198 ataio->cmd.sector_count = 1;
2199 ataio->cmd.sector_count_exp = 0;
2200 ataio->cmd.lba_low = 0x10;
2201 ataio->cmd.lba_mid = 0;
2202 ataio->cmd.lba_mid_exp = 0;
2205 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2206 ccb->ccb_h.recovery_slot = i;
2207 ccb->ccb_h.func_code = XPT_SCSI_IO;
2208 ccb->ccb_h.flags = CAM_DIR_IN;
2209 ccb->ccb_h.status = 0;
2210 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2211 csio = &ccb->csio;
2212 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2213 csio->dxfer_len = ch->hold[i]->csio.sense_len;
2214 csio->cdb_len = 6;
2215 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2216 csio->cdb_io.cdb_bytes[0] = 0x03;
2217 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2220 ch->recoverycmd = 1;
2221 xpt_freeze_simq(ch->sim, 1);
2232 ch->recoverycmd = 0;
2234 data = ccb->ataio.data_ptr;
2235 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2237 for (i = 0; i < ch->numslots; i++) {
2238 if (!ch->hold[i])
2240 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2243 res = &ch->hold[i]->ataio.res;
2244 res->status = data[2];
2245 res->error = data[3];
2246 res->lba_low = data[4];
2247 res->lba_mid = data[5];
2248 res->lba_high = data[6];
2249 res->device = data[7];
2250 res->lba_low_exp = data[8];
2251 res->lba_mid_exp = data[9];
2252 res->lba_high_exp = data[10];
2253 res->sector_count = data[12];
2254 res->sector_count_exp = data[13];
2256 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2257 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2259 ahci_done(ch, ch->hold[i]);
2260 ch->hold[i] = NULL;
2261 ch->numhslots--;
2264 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2265 device_printf(ch->dev, "Error while READ LOG EXT\n");
2267 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n");
2269 for (i = 0; i < ch->numslots; i++) {
2270 if (!ch->hold[i])
2272 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2274 ahci_done(ch, ch->hold[i]);
2275 ch->hold[i] = NULL;
2276 ch->numhslots--;
2279 free(ccb->ataio.data_ptr, M_AHCI);
2281 xpt_release_simq(ch->sim, TRUE);
2289 ch->recoverycmd = 0;
2291 i = ccb->ccb_h.recovery_slot;
2292 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2293 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2295 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2296 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2298 ahci_done(ch, ch->hold[i]);
2299 ch->hold[i] = NULL;
2300 ch->numhslots--;
2302 xpt_release_simq(ch->sim, TRUE);
2308 u_int32_t cmd;
2311 if (ch->start)
2312 ch->start(ch);
2315 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2317 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2318 /* Configure FIS-based switching if supported. */
2319 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2320 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2321 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2322 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2325 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2326 cmd &= ~AHCI_P_CMD_PMA;
2327 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2328 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2334 u_int32_t cmd;
2335 int timeout;
2338 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2339 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2341 timeout = 0;
2344 if (timeout++ > 50000) {
2345 device_printf(ch->dev, "stopping AHCI engine failed\n");
2348 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2349 ch->eslots = 0;
2355 u_int32_t cmd;
2356 int timeout;
2359 if (ch->caps & AHCI_CAP_SCLO) {
2360 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2361 cmd |= AHCI_P_CMD_CLO;
2362 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2363 timeout = 0;
2366 if (timeout++ > 50000) {
2367 device_printf(ch->dev, "executing CLO failed\n");
2370 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2377 u_int32_t cmd;
2378 int timeout;
2381 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2382 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2384 timeout = 0;
2387 if (timeout++ > 50000) {
2388 device_printf(ch->dev, "stopping AHCI FR engine failed\n");
2391 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2397 u_int32_t cmd;
2400 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2401 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2407 int timeout = 0;
2410 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2412 if (timeout > t) {
2414 device_printf(ch->dev,
2422 timeout++;
2425 device_printf(ch->dev, "AHCI reset: device ready after %dms\n",
2426 timeout + t0);
2435 if (ch->resetting == 0)
2437 ch->resetting--;
2438 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0,
2439 (310 - ch->resetting) * 100) == 0) {
2440 ch->resetting = 0;
2442 xpt_release_simq(ch->sim, TRUE);
2445 if (ch->resetting == 0) {
2448 xpt_release_simq(ch->sim, TRUE);
2451 callout_schedule(&ch->reset_timer, hz / 10);
2457 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev));
2460 xpt_freeze_simq(ch->sim, 1);
2462 device_printf(ch->dev, "AHCI reset...\n");
2464 if (ch->resetting) {
2465 ch->resetting = 0;
2466 callout_stop(&ch->reset_timer);
2467 xpt_release_simq(ch->sim, TRUE);
2470 if (ch->frozen) {
2471 union ccb *fccb = ch->frozen;
2472 ch->frozen = NULL;
2473 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2474 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2475 xpt_freeze_devq(fccb->ccb_h.path, 1);
2476 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2482 for (i = 0; i < ch->numslots; i++) {
2484 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2487 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2489 for (i = 0; i < ch->numslots; i++) {
2490 if (!ch->hold[i])
2492 ahci_done(ch, ch->hold[i]);
2493 ch->hold[i] = NULL;
2494 ch->numhslots--;
2496 if (ch->toslots != 0)
2497 xpt_release_simq(ch->sim, TRUE);
2498 ch->eslots = 0;
2499 ch->toslots = 0;
2500 ch->wrongccs = 0;
2501 ch->fatalerr = 0;
2503 xpt_async(AC_BUS_RESET, ch->path, NULL);
2505 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2509 device_printf(ch->dev,
2511 ch->devices = 0;
2513 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2514 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2516 xpt_release_simq(ch->sim, TRUE);
2520 device_printf(ch->dev, "AHCI reset: device found\n");
2526 ch->resetting = 310;
2528 ch->devices = 1;
2530 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2531 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2534 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2535 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2536 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2537 if (ch->resetting)
2538 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch);
2541 xpt_release_simq(ch->sim, TRUE);
2548 u_int8_t *fis = &ctp->cfis[0];
2552 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2553 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2556 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2557 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2560 fis[5] = ccb->csio.dxfer_len;
2561 fis[6] = ccb->csio.dxfer_len >> 8;
2565 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2566 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2567 ctp->acmd, ccb->csio.cdb_len);
2568 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2569 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2571 fis[2] = ccb->ataio.cmd.command;
2572 fis[3] = ccb->ataio.cmd.features;
2573 fis[4] = ccb->ataio.cmd.lba_low;
2574 fis[5] = ccb->ataio.cmd.lba_mid;
2575 fis[6] = ccb->ataio.cmd.lba_high;
2576 fis[7] = ccb->ataio.cmd.device;
2577 fis[8] = ccb->ataio.cmd.lba_low_exp;
2578 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2579 fis[10] = ccb->ataio.cmd.lba_high_exp;
2580 fis[11] = ccb->ataio.cmd.features_exp;
2581 fis[12] = ccb->ataio.cmd.sector_count;
2582 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2586 fis[13] = ccb->ataio.cmd.sector_count_exp;
2587 if (ccb->ataio.ata_flags & ATA_FLAG_ICC)
2588 fis[14] = ccb->ataio.icc;
2590 if (ccb->ataio.ata_flags & ATA_FLAG_AUX) {
2591 fis[16] = ccb->ataio.aux & 0xff;
2592 fis[17] = (ccb->ataio.aux >> 8) & 0xff;
2593 fis[18] = (ccb->ataio.aux >> 16) & 0xff;
2594 fis[19] = (ccb->ataio.aux >> 24) & 0xff;
2597 fis[15] = ccb->ataio.cmd.control;
2606 int timeout, timeoutslot, found = 0;
2609 * Wait for "connect well", up to 100ms by default and
2610 * up to 500ms for devices with the SLOWDEV quirk.
2612 timeoutslot = ((ch->quirks & AHCI_Q_SLOWDEV) ? 5000 : 1000);
2613 for (timeout = 0; timeout < timeoutslot; timeout++) {
2614 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2623 device_printf(ch->dev, "SATA offline status=%08x\n",
2628 if (found == 0 && timeout >= 100)
2632 if (timeout >= timeoutslot || !found) {
2634 device_printf(ch->dev,
2635 "SATA connect timeout time=%dus status=%08x\n",
2636 timeout * 100, status);
2641 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2642 timeout * 100, status);
2645 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2655 if (ch->listening) {
2656 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2658 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2659 ch->listening = 0;
2661 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2671 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2676 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2677 detval | val | ((ch->pm_level > 0) ? 0 :
2680 if (ch->caps & AHCI_CAP_SSS) {
2681 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2683 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2684 ch->listening = 1;
2685 } else if (ch->pm_level > 0)
2686 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2696 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2697 ccb->ccb_h.status = CAM_TID_INVALID;
2699 return (-1);
2701 if (ccb->ccb_h.target_lun != 0) {
2702 ccb->ccb_h.status = CAM_LUN_INVALID;
2704 return (-1);
2714 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2715 ccb->ccb_h.func_code));
2718 switch (ccb->ccb_h.func_code) {
2724 if (ch->devices == 0 ||
2725 (ch->pm_present == 0 &&
2726 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2727 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2730 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2734 ch->frozen = ccb;
2736 xpt_freeze_simq(ch->sim, 1);
2743 ccb->ccb_h.status = CAM_REQ_INVALID;
2747 struct ccb_trans_settings *cts = &ccb->cts;
2752 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2753 d = &ch->curr[ccb->ccb_h.target_id];
2755 d = &ch->user[ccb->ccb_h.target_id];
2756 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2757 d->revision = cts->xport_specific.sata.revision;
2758 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2759 d->mode = cts->xport_specific.sata.mode;
2760 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2761 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2762 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2763 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2764 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2765 ch->pm_present = cts->xport_specific.sata.pm_present;
2766 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2767 d->atapi = cts->xport_specific.sata.atapi;
2768 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2769 d->caps = cts->xport_specific.sata.caps;
2770 ccb->ccb_h.status = CAM_REQ_CMP;
2776 struct ccb_trans_settings *cts = &ccb->cts;
2782 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2783 d = &ch->curr[ccb->ccb_h.target_id];
2785 d = &ch->user[ccb->ccb_h.target_id];
2786 cts->protocol = PROTO_UNSPECIFIED;
2787 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2788 cts->transport = XPORT_SATA;
2789 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2790 cts->proto_specific.valid = 0;
2791 cts->xport_specific.sata.valid = 0;
2792 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2793 (ccb->ccb_h.target_id == 15 ||
2794 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2795 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2797 cts->xport_specific.sata.revision =
2799 cts->xport_specific.sata.valid |=
2802 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2803 if (ch->pm_level) {
2804 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2805 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2806 if (ch->caps2 & AHCI_CAP2_APST)
2807 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2809 if ((ch->caps & AHCI_CAP_SNCQ) &&
2810 (ch->quirks & AHCI_Q_NOAA) == 0)
2811 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2812 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2813 cts->xport_specific.sata.caps &=
2814 ch->user[ccb->ccb_h.target_id].caps;
2815 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2817 cts->xport_specific.sata.revision = d->revision;
2818 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2819 cts->xport_specific.sata.caps = d->caps;
2820 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2822 cts->xport_specific.sata.mode = d->mode;
2823 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2824 cts->xport_specific.sata.bytecount = d->bytecount;
2825 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2826 cts->xport_specific.sata.pm_present = ch->pm_present;
2827 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2828 cts->xport_specific.sata.tags = d->tags;
2829 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2830 cts->xport_specific.sata.atapi = d->atapi;
2831 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2832 ccb->ccb_h.status = CAM_REQ_CMP;
2838 ccb->ccb_h.status = CAM_REQ_CMP;
2842 ccb->ccb_h.status = CAM_REQ_INVALID;
2846 struct ccb_pathinq *cpi = &ccb->cpi;
2848 cpi->version_num = 1; /* XXX??? */
2849 cpi->hba_inquiry = PI_SDTR_ABLE;
2850 if (ch->caps & AHCI_CAP_SNCQ)
2851 cpi->hba_inquiry |= PI_TAG_ABLE;
2852 if (ch->caps & AHCI_CAP_SPM)
2853 cpi->hba_inquiry |= PI_SATAPM;
2854 cpi->target_sprt = 0;
2855 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
2856 if ((ch->quirks & AHCI_Q_NOAUX) == 0)
2857 cpi->hba_misc |= PIM_ATA_EXT;
2858 cpi->hba_eng_cnt = 0;
2859 if (ch->caps & AHCI_CAP_SPM)
2860 cpi->max_target = 15;
2862 cpi->max_target = 0;
2863 cpi->max_lun = 0;
2864 cpi->initiator_id = 0;
2865 cpi->bus_id = cam_sim_bus(sim);
2866 cpi->base_transfer_speed = 150000;
2867 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2868 strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2869 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2870 cpi->unit_number = cam_sim_unit(sim);
2871 cpi->transport = XPORT_SATA;
2872 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2873 cpi->protocol = PROTO_ATA;
2874 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2875 cpi->maxio = ctob(AHCI_SG_ENTRIES - 1);
2877 if (ch->quirks & AHCI_Q_MAXIO_64K)
2878 cpi->maxio = min(cpi->maxio, 128 * 512);
2879 cpi->hba_vendor = ch->vendorid;
2880 cpi->hba_device = ch->deviceid;
2881 cpi->hba_subvendor = ch->subvendorid;
2882 cpi->hba_subdevice = ch->subdeviceid;
2883 cpi->ccb_h.status = CAM_REQ_CMP;
2887 ccb->ccb_h.status = CAM_REQ_INVALID;
2900 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
2903 if (ch->resetting != 0 &&
2904 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2905 ch->resetpolldiv = 1000;