Lines Matching defs:ctlr
114 struct ahci_controller *ctlr = device_get_softc(dev);
116 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
118 if (ctlr->ccc) {
119 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
120 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
121 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
124 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
129 ctlr->ccc, ctlr->cccv);
133 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
134 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
141 struct ahci_controller *ctlr = device_get_softc(dev);
146 if ((ATA_INL(ctlr->r_mem, AHCI_VS) >= 0x00010200) &&
147 (ATA_INL(ctlr->r_mem, AHCI_CAP2) & AHCI_CAP2_BOH) &&
148 ((v = ATA_INL(ctlr->r_mem, AHCI_BOHC)) & AHCI_BOHC_OOS) == 0) {
150 ATA_OUTL(ctlr->r_mem, AHCI_BOHC, v | AHCI_BOHC_OOS);
155 v = ATA_INL(ctlr->r_mem, AHCI_BOHC);
164 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
166 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
169 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
177 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
179 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) {
187 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps);
196 struct ahci_controller *ctlr = device_get_softc(dev);
201 ctlr->dev = dev;
202 ctlr->ccc = 0;
204 device_get_unit(dev), "ccc", &ctlr->ccc);
205 mtx_init(&ctlr->ch_mtx, "AHCI channels lock", NULL, MTX_DEF);
208 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
209 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
210 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
211 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
212 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
216 if ((error = rman_manage_region(&ctlr->sc_iomem,
217 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
219 rman_fini(&ctlr->sc_iomem);
223 version = ATA_INL(ctlr->r_mem, AHCI_VS);
224 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
226 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
227 if (ctlr->caps & AHCI_CAP_EMS)
228 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
230 if (ctlr->quirks & AHCI_Q_FORCE_PI) {
237 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1;
240 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask);
245 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
248 if ((ctlr->quirks & AHCI_Q_ALTSIG) &&
249 (ctlr->caps & AHCI_CAP_SPM) == 0)
250 ctlr->quirks |= AHCI_Q_NOBSYRES;
252 if (ctlr->quirks & AHCI_Q_1CH) {
253 ctlr->caps &= ~AHCI_CAP_NPMASK;
254 ctlr->ichannels &= 0x01;
256 if (ctlr->quirks & AHCI_Q_2CH) {
257 ctlr->caps &= ~AHCI_CAP_NPMASK;
258 ctlr->caps |= 1;
259 ctlr->ichannels &= 0x03;
261 if (ctlr->quirks & AHCI_Q_4CH) {
262 ctlr->caps &= ~AHCI_CAP_NPMASK;
263 ctlr->caps |= 3;
264 ctlr->ichannels &= 0x0f;
266 ctlr->channels = MAX(flsl(ctlr->ichannels),
267 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
268 if (ctlr->quirks & AHCI_Q_NOPMP)
269 ctlr->caps &= ~AHCI_CAP_SPM;
270 if (ctlr->quirks & AHCI_Q_NONCQ)
271 ctlr->caps &= ~AHCI_CAP_SNCQ;
272 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
273 ctlr->ccc = 0;
274 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
278 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
281 ctlr->dma_coherent ? BUS_DMA_COHERENT : 0, NULL, NULL,
282 &ctlr->dma_tag)) {
284 rman_fini(&ctlr->sc_iomem);
292 bus_dma_tag_destroy(ctlr->dma_tag);
294 rman_fini(&ctlr->sc_iomem);
299 for (u = ctlr->ichannels; u != 0; u >>= 1)
301 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
303 "direct", &ctlr->direct);
305 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
310 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
313 (ctlr->caps & AHCI_CAP_SPM) ?
315 (ctlr->caps & AHCI_CAP_FBSS) ?
317 if (ctlr->quirks != 0) {
318 device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
323 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
324 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
325 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
326 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
327 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
328 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
329 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
330 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
334 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
335 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
336 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
337 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
338 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
339 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
340 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
341 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
342 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
343 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
344 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
348 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
349 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
350 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
351 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
352 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
353 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
356 for (unit = 0; unit < ctlr->channels; unit++) {
363 if ((ctlr->ichannels & (1 << unit)) == 0)
367 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
376 int em = (ctlr->caps & AHCI_CAP_EMS) != 0;
393 struct ahci_controller *ctlr = device_get_softc(dev);
402 for (i = 0; i < ctlr->numirqs; i++) {
403 if (ctlr->irqs[i].r_irq) {
404 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
405 ctlr->irqs[i].handle);
407 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
410 bus_dma_tag_destroy(ctlr->dma_tag);
412 rman_fini(&ctlr->sc_iomem);
414 mtx_destroy(&ctlr->ch_mtx);
421 struct ahci_controller *ctlr = device_get_softc(dev);
424 if (ctlr->r_mem)
425 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
426 if (ctlr->r_msix_table)
428 ctlr->r_msix_tab_rid, ctlr->r_msix_table);
429 if (ctlr->r_msix_pba)
431 ctlr->r_msix_pba_rid, ctlr->r_msix_pba);
433 ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL;
439 struct ahci_controller *ctlr = device_get_softc(dev);
443 if (ctlr->numirqs > 1 &&
444 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
446 ctlr->numirqs = 1;
450 if (ctlr->numirqs > AHCI_MAX_IRQS) {
452 ctlr->numirqs, AHCI_MAX_IRQS);
453 ctlr->numirqs = AHCI_MAX_IRQS;
457 for (i = 0; i < ctlr->numirqs; i++) {
458 ctlr->irqs[i].ctlr = ctlr;
459 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
460 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi)
461 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
462 else if (ctlr->numirqs == 1 || i >= ctlr->channels ||
463 (ctlr->ccc && i == ctlr->cccv))
464 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
465 else if (ctlr->channels > ctlr->numirqs &&
466 i == ctlr->numirqs - 1)
467 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
469 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
470 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
471 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
475 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
476 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
477 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
479 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
484 if (ctlr->numirqs > 1) {
485 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
486 ctlr->irqs[i].handle,
487 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
501 struct ahci_controller *ctlr = irq->ctlr;
508 if (ctlr->ccc)
509 is = ctlr->ichannels;
511 is = ATA_INL(ctlr->r_mem, AHCI_IS);
514 is = ATA_INL(ctlr->r_mem, AHCI_IS);
518 if (ctlr->ccc)
519 ise = 1 << ctlr->cccv;
521 if (ctlr->quirks & AHCI_Q_EDGEIS)
524 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
525 for (; unit < ctlr->channels; unit++) {
527 (arg = ctlr->interrupt[unit].argument)) {
528 ctlr->interrupt[unit].function(arg);
531 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
532 if ((arg = ctlr->interrupt[unit].argument)) {
533 ctlr->interrupt[unit].function(arg);
538 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
539 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
540 ATA_RBL(ctlr->r_mem, AHCI_IS);
550 struct ahci_controller *ctlr = irq->ctlr;
555 if ((arg = ctlr->interrupt[unit].argument))
556 ctlr->interrupt[unit].function(arg);
558 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
559 ATA_RBL(ctlr->r_mem, AHCI_IS);
566 struct ahci_controller *ctlr = irq->ctlr;
572 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
573 if ((arg = ctlr->interrupt[unit].argument))
574 ctlr->interrupt[unit].function(arg);
575 ATA_RBL(ctlr->r_mem, AHCI_IS);
582 struct ahci_controller *ctlr = device_get_softc(dev);
592 unit -= ctlr->channels;
602 offset = ctlr->remap_offset + unit * ctlr->remap_size;
603 size = ctlr->remap_size;
607 } else if ((ctlr->caps & AHCI_CAP_EMS) == 0) {
613 offset = (ctlr->emloc & 0xffff0000) >> 14;
614 size = (ctlr->emloc & 0x0000ffff) << 2;
616 if (*rid == 2 && (ctlr->capsem &
623 st = rman_get_start(ctlr->r_mem);
624 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
629 bsh = rman_get_bushandle(ctlr->r_mem);
630 bst = rman_get_bustag(ctlr->r_mem);
638 res = ctlr->irqs[0].r_irq;
665 struct ahci_controller *ctlr = device_get_softc(dev);
672 ctlr->interrupt[unit].function = function;
673 ctlr->interrupt[unit].argument = argument;
681 struct ahci_controller *ctlr = device_get_softc(dev);
684 ctlr->interrupt[unit].function = NULL;
685 ctlr->interrupt[unit].argument = NULL;
717 struct ahci_controller *ctlr = device_get_softc(dev);
719 return (ctlr->dma_tag);
725 struct ahci_controller *ctlr = device_get_softc(dev);
727 mtx_lock(&ctlr->ch_mtx);
728 ctlr->ch[ch->unit] = ch;
729 mtx_unlock(&ctlr->ch_mtx);
735 struct ahci_controller *ctlr = device_get_softc(dev);
737 mtx_lock(&ctlr->ch_mtx);
739 ctlr->ch[ch->unit] = NULL;
741 mtx_unlock(&ctlr->ch_mtx);
747 struct ahci_controller *ctlr = device_get_softc(dev);
751 mtx_lock(&ctlr->ch_mtx);
752 ch = ctlr->ch[n];
755 mtx_unlock(&ctlr->ch_mtx);
802 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
812 ch->caps = ctlr->caps;
813 ch->caps2 = ctlr->caps2;
814 ch->start = ctlr->ch_start;
815 ch->quirks = ctlr->quirks;
816 ch->vendorid = ctlr->vendorid;
817 ch->deviceid = ctlr->deviceid;
818 ch->subvendorid = ctlr->subvendorid;
819 ch->subdeviceid = ctlr->subdeviceid;
830 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
856 version = ATA_INL(ctlr->r_mem, AHCI_VS);
857 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
882 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
2457 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev));
2535 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2536 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));