Lines Matching +full:0 +full:x1f0000
31 #define AE_MASTER_REG 0x1400
33 #define AE_MASTER_SOFT_RESET 0x1 /* Reset adapter. */
34 #define AE_MASTER_MTIMER_EN 0x2 /* Unknown. */
35 #define AE_MASTER_IMT_EN 0x4 /* Interrupt moderation timer enable. */
36 #define AE_MASTER_MANUAL_INT 0x8 /* Software manual interrupt. */
38 #define AE_MASTER_REVNUM_MASK 0xff
40 #define AE_MASTER_DEVID_MASK 0xff
45 #define AE_ISR_REG 0x1600
46 #define AE_ISR_TIMER 0x00000001 /* Counter expired. */
47 #define AE_ISR_MANUAL 0x00000002 /* Manual interrupt occuried. */
48 #define AE_ISR_RXF_OVERFLOW 0x00000004 /* RxF overflow occuried. */
49 #define AE_ISR_TXF_UNDERRUN 0x00000008 /* TxF underrun occuried. */
50 #define AE_ISR_TXS_OVERFLOW 0x00000010 /* TxS overflow occuried. */
51 #define AE_ISR_RXS_OVERFLOW 0x00000020 /* Internal RxS ring overflow. */
52 #define AE_ISR_LINK_CHG 0x00000040 /* Link state changed. */
53 #define AE_ISR_TXD_UNDERRUN 0x00000080 /* TxD underrun occuried. */
54 #define AE_ISR_RXD_OVERFLOW 0x00000100 /* RxD overflow occuried. */
55 #define AE_ISR_DMAR_TIMEOUT 0x00000200 /* DMA read timeout. */
56 #define AE_ISR_DMAW_TIMEOUT 0x00000400 /* DMA write timeout. */
57 #define AE_ISR_PHY 0x00000800 /* PHY interrupt. */
58 #define AE_ISR_TXS_UPDATED 0x00010000 /* Tx status updated. */
59 #define AE_ISR_RXD_UPDATED 0x00020000 /* Rx status updated. */
60 #define AE_ISR_TX_EARLY 0x00040000 /* TxMAC started transmit. */
61 #define AE_ISR_FIFO_UNDERRUN 0x01000000 /* FIFO underrun. */
62 #define AE_ISR_FRAME_ERROR 0x02000000 /* Frame receive error. */
63 #define AE_ISR_FRAME_SUCCESS 0x04000000 /* Frame receive success. */
64 #define AE_ISR_CRC_ERROR 0x08000000 /* CRC error occuried. */
65 #define AE_ISR_PHY_LINKDOWN 0x10000000 /* PHY link down. */
66 #define AE_ISR_DISABLE 0x80000000 /* Disable interrupts. */
75 #define AE_IMR_REG 0x1604
84 #define AE_EADDR0_REG 0x1488 /* 5 - 2 bytes */
85 #define AE_EADDR1_REG 0x148c /* 1 - 0 bytes */
92 #define AE_DESC_ADDR_HI_REG 0x1540 /* High 32 bits of ring base address. */
93 #define AE_RXD_ADDR_LO_REG 0x1554 /* Low 32 bits of RxD ring address. */
94 #define AE_TXD_ADDR_LO_REG 0x1544 /* Low 32 bits of TxD ring address. */
95 #define AE_TXS_ADDR_LO_REG 0x154c /* Low 32 bits of TxS ring address. */
96 #define AE_RXD_COUNT_REG 0x1558 /* Number of RxD descriptors in ring.
100 #define AE_TXD_BUFSIZE_REG 0x1548 /* Size of TxD ring in 4-byte units.
102 #define AE_TXS_COUNT_REG 0x1550 /* Number of TxS descriptors in ring.
121 #define AE_IFG_REG 0x1484
123 #define AE_IFG_TXIPG_DEFAULT 0x60 /* 96-bit IFG time. */
124 #define AE_IFG_TXIPG_SHIFT 0
125 #define AE_IFG_TXIPG_MASK 0x7f
127 #define AE_IFG_RXIPG_DEFAULT 0x50 /* 80-bit IFG time. */
129 #define AE_IFG_RXIPG_MASK 0xff00
131 #define AE_IFG_IPGR1_DEFAULT 0x40 /* Carrier-sense window. */
133 #define AE_IFG_IPGR1_MASK 0x7f0000
135 #define AE_IFG_IPGR2_DEFAULT 0x60 /* IFG window. */
137 #define AE_IFG_IPGR2_MASK 0x7f000000
142 #define AE_HDPX_REG 0x1498
145 #define AE_HDPX_LCOL_SHIFT 0
146 #define AE_HDPX_LCOL_MASK 0x000003ff
147 #define AE_HDPX_LCOL_DEFAULT 0x37
151 #define AE_HDPX_RETRY_MASK 0x0000f000
152 #define AE_HDPX_RETRY_DEFAULT 0x0f
156 #define AE_HDPX_ABEBT_MASK 0x00f00000
157 #define AE_HDPX_ABEBT_DEFAULT 0x0a
161 #define AE_HDPX_JAMIPG_MASK 0x0f000000
162 #define AE_HDPX_JAMIPG_DEFAULT 0x07
165 #define AE_HDPX_EXC_EN 0x00010000
167 #define AE_HDPX_NO_BACK_C 0x00020000
169 #define AE_HDPX_NO_BACK_P 0x00040000
171 #define AE_HDPX_ABEBE 0x00080000
176 #define AE_IMT_REG 0x1408 /* Timer value in 2 us units. */
184 #define AE_ICT_REG 0x140e /* Maximum time allowed to clear
191 #define AE_MTU_REG 0x149c /* MTU size in bytes. */
196 #define AE_CUT_THRESH_REG 0x1590 /* Cut-through threshold in unknown units. */
197 #define AE_CUT_THRESH_DEFAULT 0x177
202 #define AE_FLOW_THRESH_HI_REG 0x15a8 /* High watermark of RxD
204 #define AE_FLOW_THRESH_LO_REG 0x15aa /* Lower watermark of RxD
210 #define AE_MB_TXD_IDX_REG 0x15f0 /* TxD read index. */
211 #define AE_MB_RXD_IDX_REG 0x15f4 /* RxD write index. */
216 #define AE_DMAREAD_REG 0x1580 /* Read DMA configuration register. */
218 #define AE_DMAWRITE_REG 0x15a0 /* Write DMA configuration register. */
224 #define AE_MAC_REG 0x1480
226 #define AE_MAC_TX_EN 0x00000001 /* Enable transmit. */
227 #define AE_MAC_RX_EN 0x00000002 /* Enable receive. */
228 #define AE_MAC_TX_FLOW_EN 0x00000004 /* Enable Tx flow control. */
229 #define AE_MAC_RX_FLOW_EN 0x00000008 /* Enable Rx flow control. */
230 #define AE_MAC_LOOPBACK 0x00000010 /* Loopback at MII. */
231 #define AE_MAC_FULL_DUPLEX 0x00000020 /* Enable full-duplex. */
232 #define AE_MAC_TX_CRC_EN 0x00000040 /* Enable CRC generation. */
233 #define AE_MAC_TX_AUTOPAD 0x00000080 /* Pad short frames. */
234 #define AE_MAC_PREAMBLE_MASK 0x00003c00 /* Preamble length. */
236 #define AE_MAC_PREAMBLE_DEFAULT 0x07 /* By standard. */
237 #define AE_MAC_RMVLAN_EN 0x00004000 /* Remove VLAN tags in
239 #define AE_MAC_PROMISC_EN 0x00008000 /* Enable promiscue mode. */
240 #define AE_MAC_TX_MAXBACKOFF 0x00100000 /* Unknown. */
241 #define AE_MAC_MCAST_EN 0x02000000 /* Pass all multicast frames. */
242 #define AE_MAC_BCAST_EN 0x04000000 /* Pass all broadcast frames. */
243 #define AE_MAC_CLK_PHY 0x08000000 /* If 1 uses loopback clock
244 PHY, if 0 - system clock. */
245 #define AE_HALFBUF_MASK 0xf0000000 /* Half-duplex retry buffer. */
252 #define AE_MDIO_REG 0x1414 …
253 #define AE_MDIO_DATA_MASK 0xffff
254 #define AE_MDIO_DATA_SHIFT 0
255 #define AE_MDIO_REGADDR_MASK 0x1f0000
257 #define AE_MDIO_READ 0x00200000 /* Read operation. */
258 #define AE_MDIO_SUP_PREAMBLE 0x00400000 /* Suppress preamble. */
259 #define AE_MDIO_START 0x00800000 /* Initiate MDIO transfer. */
261 #define AE_MDIO_CLK_MASK 0x07000000 /* Clock selection. */
262 #define AE_MDIO_CLK_25_4 0 /* Dividers? */
269 #define AE_MDIO_BUSY 0x08000000 /* MDIO is busy. */
274 #define AE_IDLE_REG 0x1410
288 #define AE_REG_MHT0 0x1490
289 #define AE_REG_MHT1 0x1494
294 #define AE_WOL_REG 0x14a0
295 #define AE_WOL_MAGIC 0x00000004
296 #define AE_WOL_MAGIC_PME 0x00000008
297 #define AE_WOL_LNKCHG 0x00000010
298 #define AE_WOL_LNKCHG_PME 0x00000020
303 #define AE_PCIE_LTSSM_TESTMODE_REG 0x12fc
304 #define AE_PCIE_LTSSM_TESTMODE_DEFAULT 0x6500
305 #define AE_PCIE_DLL_TX_CTRL_REG 0x1104
306 #define AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK 0x0400
307 #define AE_PCIE_DLL_TX_CTRL_DEFAULT 0x0568
308 #define AE_PCIE_PHYMISC_REG 0x1000
309 #define AE_PCIE_PHYMISC_FORCE_RCV_DET 0x4
314 #define AE_PHY_ENABLE_REG 0x140c
320 #define AE_VPD_CAP_REG 0x6c /* Command register. */
321 #define AE_VPD_CAP_ID_MASK 0xff
322 #define AE_VPD_CAP_ID_SHIFT 0
323 #define AE_VPD_CAP_NEXT_MASK 0xff00
325 #define AE_VPD_CAP_ADDR_MASK 0x7fff0000
327 #define AE_VPD_CAP_DONE 0x80000000
329 #define AE_VPD_DATA_REG 0x70 /* Data register. */
332 #define AE_VPD_SIG_MASK 0xff
333 #define AE_VPD_SIG 0x5a /* VPD block signature. */
339 #define AE_SPICTL_REG 0x200
340 #define AE_SPICTL_VPD_EN 0x2000 /* Enable VPD. */
345 #define AE_PHY_DBG_ADDR 0x1d
346 #define AE_PHY_DBG_DATA 0x1e
347 #define AE_PHY_DBG_POWERSAVE 0x1000
352 #define AE_TXD_INSERT_VTAG 0x8000 /* Insert VLAN tag on transfer. */
357 #define AE_TXS_SUCCESS 0x0001 /* Packed transmitted successfully. */
358 #define AE_TXS_BCAST 0x0002 /* Transmitted broadcast frame. */
359 #define AE_TXS_MCAST 0x0004 /* Transmitted multicast frame. */
360 #define AE_TXS_PAUSE 0x0008 /* Transmitted pause frame. */
361 #define AE_TXS_CTRL 0x0010 /* Transmitted control frame. */
362 #define AE_TXS_DEFER 0x0020 /* Frame transmitted with defer. */
363 #define AE_TXS_EXCDEFER 0x0040 /* Excessive collision. */
364 #define AE_TXS_SINGLECOL 0x0080 /* Single collision occuried. */
365 #define AE_TXS_MULTICOL 0x0100 /* Multiple collisions occuried. */
366 #define AE_TXS_LATECOL 0x0200 /* Late collision occuried. */
367 #define AE_TXS_ABORTCOL 0x0400 /* Frame abort due to collisions. */
368 #define AE_TXS_UNDERRUN 0x0800 /* Tx SRAM underrun occuried. */
369 #define AE_TXS_UPDATE 0x8000
374 #define AE_RXD_SUCCESS 0x0001
375 #define AE_RXD_BCAST 0x0002 /* Broadcast frame received. */
376 #define AE_RXD_MCAST 0x0004 /* Multicast frame received. */
377 #define AE_RXD_PAUSE 0x0008 /* Pause frame received. */
378 #define AE_RXD_CTRL 0x0010 /* Control frame received. */
379 #define AE_RXD_CRCERR 0x0020 /* Invalid frame CRC. */
380 #define AE_RXD_CODEERR 0x0040 /* Invalid frame opcode. */
381 #define AE_RXD_RUNT 0x0080 /* Runt frame received. */
382 #define AE_RXD_FRAG 0x0100 /* Collision fragment received. */
383 #define AE_RXD_TRUNC 0x0200 /* The frame was truncated due
385 #define AE_RXD_ALIGN 0x0400 /* Frame alignment error. */
386 #define AE_RXD_HAS_VLAN 0x0800 /* VLAN tag present. */
387 #define AE_RXD_UPDATE 0x8000