Lines Matching defs:sc
104 static void ae_pcie_init(ae_softc_t *sc);
105 static void ae_phy_reset(ae_softc_t *sc);
106 static void ae_phy_init(ae_softc_t *sc);
107 static int ae_reset(ae_softc_t *sc);
109 static int ae_init_locked(ae_softc_t *sc);
116 static void ae_retrieve_address(ae_softc_t *sc);
119 static int ae_alloc_rings(ae_softc_t *sc);
120 static void ae_dma_free(ae_softc_t *sc);
123 static void ae_powersave_disable(ae_softc_t *sc);
124 static void ae_powersave_enable(ae_softc_t *sc);
126 static unsigned int ae_tx_avail_size(ae_softc_t *sc);
127 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head);
131 static void ae_stop_rxmac(ae_softc_t *sc);
132 static void ae_stop_txmac(ae_softc_t *sc);
133 static void ae_mac_config(ae_softc_t *sc);
136 static void ae_tx_intr(ae_softc_t *sc);
137 static void ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd);
138 static void ae_rx_intr(ae_softc_t *sc);
139 static void ae_watchdog(ae_softc_t *sc);
141 static void ae_rxfilter(ae_softc_t *sc);
142 static void ae_rxvlan(ae_softc_t *sc);
144 static void ae_stop(ae_softc_t *sc);
145 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc);
146 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word);
147 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr);
148 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr);
151 static void ae_init_tunables(ae_softc_t *sc);
188 #define AE_READ_4(sc, reg) \
189 bus_read_4((sc)->mem[0], (reg))
190 #define AE_READ_2(sc, reg) \
191 bus_read_2((sc)->mem[0], (reg))
192 #define AE_READ_1(sc, reg) \
193 bus_read_1((sc)->mem[0], (reg))
194 #define AE_WRITE_4(sc, reg, val) \
195 bus_write_4((sc)->mem[0], (reg), (val))
196 #define AE_WRITE_2(sc, reg, val) \
197 bus_write_2((sc)->mem[0], (reg), (val))
198 #define AE_WRITE_1(sc, reg, val) \
199 bus_write_1((sc)->mem[0], (reg), (val))
200 #define AE_PHY_READ(sc, reg) \
201 ae_miibus_readreg(sc->dev, 0, reg)
202 #define AE_PHY_WRITE(sc, reg, val) \
203 ae_miibus_writereg(sc->dev, 0, reg, val)
237 ae_softc_t *sc;
244 sc = device_get_softc(dev); /* Automatically allocated and zeroed
246 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
247 sc->dev = dev;
252 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF);
253 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0);
254 TASK_INIT(&sc->int_task, 0, ae_int_task, sc);
255 TASK_INIT(&sc->link_task, 0, ae_link_task, sc);
259 sc->spec_mem = ae_res_spec_mem;
264 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem);
267 sc->spec_mem = NULL;
275 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) &
292 sc->spec_irq = ae_res_spec_msi;
293 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq);
296 sc->spec_irq = NULL;
299 sc->flags |= AE_FLAG_MSI;
303 if (sc->spec_irq == NULL) {
304 sc->spec_irq = ae_res_spec_irq;
305 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq);
308 sc->spec_irq = NULL;
313 ae_init_tunables(sc);
315 ae_phy_reset(sc); /* Reset PHY. */
316 error = ae_reset(sc); /* Reset the controller itself. */
320 ae_pcie_init(sc);
322 ae_retrieve_address(sc); /* Load MAC address. */
324 error = ae_alloc_rings(sc); /* Allocate ring buffers. */
328 ifp = sc->ifp = if_alloc(IFT_ETHER);
329 if_setsoftc(ifp, sc);
341 sc->flags |= AE_FLAG_PMG;
348 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange,
356 ether_ifattach(ifp, sc->eaddr);
363 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK,
364 taskqueue_thread_enqueue, &sc->tq);
365 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq",
366 device_get_nameunit(sc->dev));
371 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE,
372 ae_intr, NULL, sc, &sc->intrhand);
375 taskqueue_free(sc->tq);
376 sc->tq = NULL;
392 ae_init_tunables(ae_softc_t *sc)
398 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
399 ae_stats = &sc->stats;
401 ctx = device_get_sysctl_ctx(sc->dev);
402 root = device_get_sysctl_tree(sc->dev);
462 ae_pcie_init(ae_softc_t *sc)
465 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT);
466 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT);
470 ae_phy_reset(ae_softc_t *sc)
473 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE);
478 ae_reset(ae_softc_t *sc)
485 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET);
486 bus_barrier(sc->mem[0], AE_MASTER_REG, 4,
493 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0)
498 device_printf(sc->dev, "reset timeout.\n");
506 if (AE_READ_4(sc, AE_IDLE_REG) == 0)
511 device_printf(sc->dev, "could not enter idle state.\n");
520 ae_softc_t *sc;
522 sc = (ae_softc_t *)arg;
523 AE_LOCK(sc);
524 ae_init_locked(sc);
525 AE_UNLOCK(sc);
529 ae_phy_init(ae_softc_t *sc)
537 AE_PHY_WRITE(sc, 18, 0xc00);
542 ae_init_locked(ae_softc_t *sc)
550 AE_LOCK_ASSERT(sc);
552 ifp = sc->ifp;
555 mii = device_get_softc(sc->miibus);
557 ae_stop(sc);
558 ae_reset(sc);
559 ae_pcie_init(sc); /* Initialize PCIE stuff. */
560 ae_phy_init(sc);
561 ae_powersave_disable(sc);
566 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);
573 AE_WRITE_4(sc, AE_EADDR0_REG, val);
575 AE_WRITE_4(sc, AE_EADDR1_REG, val);
577 bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING);
578 bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT);
579 bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4);
583 addr = sc->dma_rxd_busaddr;
584 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr));
585 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
586 addr = sc->dma_txd_busaddr;
587 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
588 addr = sc->dma_txs_busaddr;
589 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr));
594 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT);
595 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4);
596 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT);
609 AE_WRITE_4(sc, AE_IFG_REG, val);
622 AE_WRITE_4(sc, AE_HDPX_REG, val);
627 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT);
628 val = AE_READ_4(sc, AE_MASTER_REG);
630 AE_WRITE_4(sc, AE_MASTER_REG, val);
635 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT);
642 AE_WRITE_2(sc, AE_MTU_REG, val);
647 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT);
652 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7);
653 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) >
660 sc->txd_cur = sc->rxd_cur = 0;
661 sc->txs_ack = sc->txd_ack = 0;
662 sc->rxd_cur = 0;
663 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur);
664 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur);
666 sc->tx_inproc = 0; /* Number of packets the chip processes now. */
667 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */
672 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN);
673 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN);
678 val = AE_READ_4(sc, AE_ISR_REG);
680 device_printf(sc->dev, "Initialization failed.\n");
687 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff);
688 AE_WRITE_4(sc, AE_ISR_REG, 0x0);
693 val = AE_READ_4(sc, AE_MASTER_REG);
694 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT);
695 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT);
700 AE_WRITE_4(sc, AE_WOL_REG, 0);
711 AE_WRITE_4(sc, AE_MAC_REG, val);
716 ae_rxfilter(sc);
717 ae_rxvlan(sc);
722 val = AE_READ_4(sc, AE_MAC_REG);
723 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN);
725 sc->flags &= ~AE_FLAG_LINK;
728 callout_reset(&sc->tick_ch, hz, ae_tick, sc);
734 device_printf(sc->dev, "Initialization complete.\n");
743 struct ae_softc *sc;
746 sc = device_get_softc(dev);
747 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__));
748 ifp = sc->ifp;
750 AE_LOCK(sc);
751 sc->flags |= AE_FLAG_DETACH;
752 ae_stop(sc);
753 AE_UNLOCK(sc);
754 callout_drain(&sc->tick_ch);
755 taskqueue_drain(sc->tq, &sc->int_task);
756 taskqueue_drain(taskqueue_swi, &sc->link_task);
759 if (sc->tq != NULL) {
760 taskqueue_drain(sc->tq, &sc->int_task);
761 taskqueue_free(sc->tq);
762 sc->tq = NULL;
764 bus_generic_detach(sc->dev);
765 ae_dma_free(sc);
766 if (sc->intrhand != NULL) {
767 bus_teardown_intr(dev, sc->irq[0], sc->intrhand);
768 sc->intrhand = NULL;
772 sc->ifp = NULL;
774 if (sc->spec_irq != NULL)
775 bus_release_resources(dev, sc->spec_irq, sc->irq);
776 if (sc->spec_mem != NULL)
777 bus_release_resources(dev, sc->spec_mem, sc->mem);
778 if ((sc->flags & AE_FLAG_MSI) != 0)
780 mtx_destroy(&sc->mtx);
788 ae_softc_t *sc;
792 sc = device_get_softc(dev);
793 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
802 AE_WRITE_4(sc, AE_MDIO_REG, val);
809 val = AE_READ_4(sc, AE_MDIO_REG);
814 device_printf(sc->dev, "phy read timeout: %d.\n", reg);
823 ae_softc_t *sc;
827 sc = device_get_softc(dev);
828 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
838 AE_WRITE_4(sc, AE_MDIO_REG, aereg);
845 aereg = AE_READ_4(sc, AE_MDIO_REG);
850 device_printf(sc->dev, "phy write timeout: %d.\n", reg);
858 ae_softc_t *sc;
860 sc = device_get_softc(dev);
861 taskqueue_enqueue(taskqueue_swi, &sc->link_task);
867 ae_softc_t *sc;
870 sc = if_getsoftc(ifp);
871 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
873 AE_LOCK(sc);
874 mii = device_get_softc(sc->miibus);
878 AE_UNLOCK(sc);
884 ae_softc_t *sc;
890 sc = if_getsoftc(ifp);
891 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
892 AE_LOCK(sc);
893 mii = device_get_softc(sc->miibus);
897 AE_UNLOCK(sc);
903 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc)
913 val = AE_READ_4(sc, AE_SPICTL_REG);
916 AE_WRITE_4(sc, AE_SPICTL_REG, val);
918 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc);
923 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word)
928 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */
934 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) &
938 val = AE_READ_4(sc, AE_VPD_CAP_REG);
943 device_printf(sc->dev, "timeout reading VPD register %d.\n",
947 *word = AE_READ_4(sc, AE_VPD_DATA_REG);
952 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr)
960 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
966 error = ae_check_eeprom_present(sc, &vpdc);
976 error = ae_vpd_read_word(sc, i, &word);
991 error = ae_vpd_read_word(sc, i, &val);
1007 device_printf(sc->dev,
1015 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr)
1021 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG);
1022 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG);
1027 device_printf(sc->dev,
1035 ae_retrieve_address(ae_softc_t *sc)
1043 error = ae_get_vpd_eaddr(sc, eaddr);
1045 error = ae_get_reg_eaddr(sc, eaddr);
1048 device_printf(sc->dev,
1055 sc->eaddr[0] = 0x02; /* U/L bit set. */
1056 sc->eaddr[1] = 0x1f;
1057 sc->eaddr[2] = 0xc6;
1058 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff;
1059 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff;
1060 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff;
1062 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff;
1063 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff;
1064 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff;
1065 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff;
1066 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff;
1067 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff;
1084 ae_alloc_rings(ae_softc_t *sc)
1092 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
1096 &sc->dma_parent_tag);
1098 device_printf(sc->dev, "could not creare parent DMA tag.\n");
1105 error = bus_dma_tag_create(sc->dma_parent_tag,
1109 &sc->dma_txd_tag);
1111 device_printf(sc->dev, "could not creare TxD DMA tag.\n");
1118 error = bus_dma_tag_create(sc->dma_parent_tag,
1122 &sc->dma_txs_tag);
1124 device_printf(sc->dev, "could not creare TxS DMA tag.\n");
1131 error = bus_dma_tag_create(sc->dma_parent_tag,
1135 &sc->dma_rxd_tag);
1137 device_printf(sc->dev, "could not creare TxS DMA tag.\n");
1144 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base,
1146 &sc->dma_txd_map);
1148 device_printf(sc->dev,
1152 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base,
1155 device_printf(sc->dev,
1159 sc->dma_txd_busaddr = busaddr;
1164 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base,
1166 &sc->dma_txs_map);
1168 device_printf(sc->dev,
1172 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base,
1175 device_printf(sc->dev,
1179 sc->dma_txs_busaddr = busaddr;
1184 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma,
1186 &sc->dma_rxd_map);
1188 device_printf(sc->dev,
1192 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map,
1193 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING,
1196 device_printf(sc->dev,
1200 sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING;
1201 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING);
1207 ae_dma_free(ae_softc_t *sc)
1210 if (sc->dma_txd_tag != NULL) {
1211 if (sc->dma_txd_busaddr != 0)
1212 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map);
1213 if (sc->txd_base != NULL)
1214 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base,
1215 sc->dma_txd_map);
1216 bus_dma_tag_destroy(sc->dma_txd_tag);
1217 sc->dma_txd_tag = NULL;
1218 sc->txd_base = NULL;
1219 sc->dma_txd_busaddr = 0;
1221 if (sc->dma_txs_tag != NULL) {
1222 if (sc->dma_txs_busaddr != 0)
1223 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map);
1224 if (sc->txs_base != NULL)
1225 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base,
1226 sc->dma_txs_map);
1227 bus_dma_tag_destroy(sc->dma_txs_tag);
1228 sc->dma_txs_tag = NULL;
1229 sc->txs_base = NULL;
1230 sc->dma_txs_busaddr = 0;
1232 if (sc->dma_rxd_tag != NULL) {
1233 if (sc->dma_rxd_busaddr != 0)
1234 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map);
1235 if (sc->rxd_base_dma != NULL)
1236 bus_dmamem_free(sc->dma_rxd_tag, sc->rxd_base_dma,
1237 sc->dma_rxd_map);
1238 bus_dma_tag_destroy(sc->dma_rxd_tag);
1239 sc->dma_rxd_tag = NULL;
1240 sc->rxd_base_dma = NULL;
1241 sc->dma_rxd_busaddr = 0;
1243 if (sc->dma_parent_tag != NULL) {
1244 bus_dma_tag_destroy(sc->dma_parent_tag);
1245 sc->dma_parent_tag = NULL;
1252 ae_softc_t *sc;
1255 sc = device_get_softc(dev);
1256 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__));
1259 AE_LOCK(sc);
1260 ae_powersave_enable(sc);
1261 AE_UNLOCK(sc);
1266 ae_powersave_disable(ae_softc_t *sc)
1270 AE_LOCK_ASSERT(sc);
1272 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0);
1273 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA);
1276 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val);
1282 ae_powersave_enable(ae_softc_t *sc)
1286 AE_LOCK_ASSERT(sc);
1291 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0);
1292 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA);
1293 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000);
1294 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2);
1295 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000);
1296 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3);
1297 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0);
1301 ae_pm_init(ae_softc_t *sc)
1309 AE_LOCK_ASSERT(sc);
1311 ifp = sc->ifp;
1312 if ((sc->flags & AE_FLAG_PMG) == 0) {
1314 AE_WRITE_4(sc, AE_WOL_REG, 0);
1322 mii = device_get_softc(sc->miibus);
1326 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \
1342 AE_WRITE_4(sc, AE_MAC_REG, val);
1345 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \
1347 AE_WRITE_4(sc, AE_MAC_REG, 0);
1350 ae_powersave_enable(sc);
1356 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG);
1358 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val);
1359 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG);
1361 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val);
1366 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1367 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1371 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1378 ae_softc_t *sc;
1380 sc = device_get_softc(dev);
1382 AE_LOCK(sc);
1383 ae_stop(sc);
1384 ae_pm_init(sc);
1385 AE_UNLOCK(sc);
1393 ae_softc_t *sc;
1395 sc = device_get_softc(dev);
1396 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1398 AE_LOCK(sc);
1399 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */
1400 if ((if_getflags(sc->ifp) & IFF_UP) != 0)
1401 ae_init_locked(sc);
1402 AE_UNLOCK(sc);
1408 ae_tx_avail_size(ae_softc_t *sc)
1412 if (sc->txd_cur >= sc->txd_ack)
1413 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack);
1415 avail = sc->txd_ack - sc->txd_cur;
1421 ae_encap(ae_softc_t *sc, struct mbuf **m_head)
1428 AE_LOCK_ASSERT(sc);
1433 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 ||
1434 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) {
1436 if_printf(sc->ifp, "No free Tx available.\n");
1441 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur);
1444 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT;
1446 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur;
1448 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur));
1450 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base +
1451 sc->txd_cur));
1452 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base);
1468 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT;
1469 if (sc->txd_cur == sc->txd_ack)
1470 sc->flags &= ~AE_FLAG_TXAVAIL;
1472 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur);
1478 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE);
1479 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT;
1480 if (sc->txs_cur == sc->txs_ack)
1481 sc->flags &= ~AE_FLAG_TXAVAIL;
1486 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD |
1488 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1497 ae_softc_t *sc;
1499 sc = if_getsoftc(ifp);
1500 AE_LOCK(sc);
1502 AE_UNLOCK(sc);
1508 ae_softc_t *sc;
1513 sc = if_getsoftc(ifp);
1514 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1515 AE_LOCK_ASSERT(sc);
1522 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0)
1531 error = ae_encap(sc, &m0);
1543 sc->tx_inproc++;
1552 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4);
1553 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */
1556 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur);
1564 ae_softc_t *sc;
1569 sc = (ae_softc_t *)arg;
1570 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1571 AE_LOCK(sc);
1573 ifp = sc->ifp;
1574 mii = device_get_softc(sc->miibus);
1577 AE_UNLOCK(sc); /* XXX: could happen? */
1581 sc->flags &= ~AE_FLAG_LINK;
1587 sc->flags |= AE_FLAG_LINK;
1597 ae_stop_rxmac(sc);
1598 ae_stop_txmac(sc);
1600 if ((sc->flags & AE_FLAG_LINK) != 0) {
1601 ae_mac_config(sc);
1606 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN);
1607 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN);
1612 val = AE_READ_4(sc, AE_MAC_REG);
1614 AE_WRITE_4(sc, AE_MAC_REG, val);
1616 AE_UNLOCK(sc);
1620 ae_stop_rxmac(ae_softc_t *sc)
1625 AE_LOCK_ASSERT(sc);
1630 val = AE_READ_4(sc, AE_MAC_REG);
1633 AE_WRITE_4(sc, AE_MAC_REG, val);
1639 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN)
1640 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0);
1646 val = AE_READ_4(sc, AE_IDLE_REG);
1652 device_printf(sc->dev, "timed out while stopping Rx MAC.\n");
1656 ae_stop_txmac(ae_softc_t *sc)
1661 AE_LOCK_ASSERT(sc);
1666 val = AE_READ_4(sc, AE_MAC_REG);
1669 AE_WRITE_4(sc, AE_MAC_REG, val);
1675 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN)
1676 AE_WRITE_1(sc, AE_DMAREAD_REG, 0);
1682 val = AE_READ_4(sc, AE_IDLE_REG);
1688 device_printf(sc->dev, "timed out while stopping Tx MAC.\n");
1692 ae_mac_config(ae_softc_t *sc)
1697 AE_LOCK_ASSERT(sc);
1699 mii = device_get_softc(sc->miibus);
1700 val = AE_READ_4(sc, AE_MAC_REG);
1707 AE_WRITE_4(sc, AE_MAC_REG, val);
1713 ae_softc_t *sc;
1716 sc = (ae_softc_t *)arg;
1717 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1719 val = AE_READ_4(sc, AE_ISR_REG);
1724 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE);
1727 taskqueue_enqueue(sc->tq, &sc->int_task);
1735 ae_softc_t *sc;
1739 sc = (ae_softc_t *)arg;
1741 AE_LOCK(sc);
1743 ifp = sc->ifp;
1745 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */
1747 AE_UNLOCK(sc);
1754 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE);
1764 ae_init_locked(sc);
1765 AE_UNLOCK(sc);
1769 ae_tx_intr(sc);
1771 ae_rx_intr(sc);
1775 AE_WRITE_4(sc, AE_ISR_REG, 0);
1777 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) {
1783 AE_UNLOCK(sc);
1787 ae_tx_intr(ae_softc_t *sc)
1794 AE_LOCK_ASSERT(sc);
1796 ifp = sc->ifp;
1805 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map,
1807 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1811 txs = sc->txs_base + sc->txs_ack;
1817 ae_update_stats_tx(flags, &sc->stats);
1822 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT;
1823 sc->flags |= AE_FLAG_TXAVAIL;
1825 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack);
1827 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n",
1833 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) +
1841 sc->tx_inproc--;
1844 if ((sc->flags & AE_FLAG_TXAVAIL) != 0)
1846 if (sc->tx_inproc < 0) {
1848 sc->tx_inproc = 0;
1851 if (sc->tx_inproc == 0)
1852 sc->wd_timer = 0; /* Unarm watchdog. */
1857 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map,
1859 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1864 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd)
1871 AE_LOCK_ASSERT(sc);
1873 ifp = sc->ifp;
1902 AE_UNLOCK(sc);
1904 AE_LOCK(sc);
1908 ae_rx_intr(ae_softc_t *sc)
1915 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
1917 AE_LOCK_ASSERT(sc);
1919 ifp = sc->ifp;
1924 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map,
1928 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur);
1934 ae_update_stats_rx(flags, &sc->stats);
1939 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT;
1942 ae_rxeof(sc, rxd);
1948 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map,
1953 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur);
1958 ae_watchdog(ae_softc_t *sc)
1962 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
1963 AE_LOCK_ASSERT(sc);
1964 ifp = sc->ifp;
1966 if (sc->wd_timer == 0 || --sc->wd_timer != 0)
1969 if ((sc->flags & AE_FLAG_LINK) == 0)
1976 ae_init_locked(sc);
1984 ae_softc_t *sc;
1987 sc = (ae_softc_t *)arg;
1988 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
1989 AE_LOCK_ASSERT(sc);
1991 mii = device_get_softc(sc->miibus);
1993 ae_watchdog(sc); /* Watchdog check. */
1994 callout_reset(&sc->tick_ch, hz, ae_tick, sc);
1998 ae_rxvlan(ae_softc_t *sc)
2003 AE_LOCK_ASSERT(sc);
2004 ifp = sc->ifp;
2005 val = AE_READ_4(sc, AE_MAC_REG);
2009 AE_WRITE_4(sc, AE_MAC_REG, val);
2024 ae_rxfilter(ae_softc_t *sc)
2030 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
2032 AE_LOCK_ASSERT(sc);
2034 ifp = sc->ifp;
2036 rxcfg = AE_READ_4(sc, AE_MAC_REG);
2049 AE_WRITE_4(sc, AE_REG_MHT0, 0);
2050 AE_WRITE_4(sc, AE_REG_MHT1, 0);
2052 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff);
2053 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff);
2054 AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2063 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]);
2064 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]);
2065 AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2071 struct ae_softc *sc;
2076 sc = if_getsoftc(ifp);
2085 AE_LOCK(sc);
2089 ae_init_locked(sc);
2091 AE_UNLOCK(sc);
2095 AE_LOCK(sc);
2098 if (((if_getflags(ifp) ^ sc->if_flags)
2100 ae_rxfilter(sc);
2102 if ((sc->flags & AE_FLAG_DETACH) == 0)
2103 ae_init_locked(sc);
2107 ae_stop(sc);
2109 sc->if_flags = if_getflags(ifp);
2110 AE_UNLOCK(sc);
2114 AE_LOCK(sc);
2116 ae_rxfilter(sc);
2117 AE_UNLOCK(sc);
2121 mii = device_get_softc(sc->miibus);
2125 AE_LOCK(sc);
2130 ae_rxvlan(sc);
2133 AE_UNLOCK(sc);
2143 ae_stop(ae_softc_t *sc)
2148 AE_LOCK_ASSERT(sc);
2150 ifp = sc->ifp;
2152 sc->flags &= ~AE_FLAG_LINK;
2153 sc->wd_timer = 0; /* Cancel watchdog. */
2154 callout_stop(&sc->tick_ch);
2159 AE_WRITE_4(sc, AE_IMR_REG, 0);
2160 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);
2165 ae_stop_txmac(sc);
2166 ae_stop_rxmac(sc);
2171 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN);
2172 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN);
2178 if (AE_READ_4(sc, AE_IDLE_REG) == 0)
2183 device_printf(sc->dev, "could not enter idle state in stop.\n");