Lines Matching full:rx
150 /** @Description BMI Rx port register map */
152 uint32_t fmbm_rcfg; /**< Rx Configuration */
153 uint32_t fmbm_rst; /**< Rx Status */
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
155 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
156 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
157 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
158 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
159 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
160 uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/
161 uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/
162 uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/
163 uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/
164 uint32_t fmbm_rpp; /**< Rx Policer Profile */
165 uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */
166 uint32_t fmbm_reth; /**< Rx Excessive Threshold */
169 /**< Rx Parse Results Array Init*/
170 uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/
171 uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/
172 uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/
173 uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/
174 uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */
176 uint32_t fmbm_rcmne; /**< Rx Frame Continuous Mode Next Engine */
188 uint32_t fmbm_rstc; /**< Rx Statistics Counters*/
189 uint32_t fmbm_rfrc; /**< Rx Frame Counter*/
190 uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/
191 uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/
192 uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/
193 uint32_t fmbm_rfdc; /**< Rx Frame Discard Counter*/
194 uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/
195 uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard nntr*/
196 uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/
198 uint32_t fmbm_rpc; /**< Rx Performance Counters*/
199 uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/
200 uint32_t fmbm_rccn; /**< Rx Cycle Counter*/
201 uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/
202 uint32_t fmbm_rrquc; /**< Rx Receive Queue Utilization cntr*/
203 uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/
204 uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/
205 uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/
207 uint32_t fmbm_rdbg; /**< Rx Debug-*/
286 uint32_t fmbm_ofwdc; /**< Rx Frames WRED Discard Counter */
300 struct fman_port_rx_bmi_regs rx; member
359 /**< Rx or Tx conf queue compare value (unused for O/H ports) */
411 E_FMAN_PORT_TYPE_RX, /**< 1G Rx port */
412 E_FMAN_PORT_TYPE_RX_10G, /**< 10G Rx port */
488 /**< For Rx ports - frames discarded by QMAN, for Tx or O/H ports -
493 /**< Number of bad Rx frames, like CRC error, Rx FIFO overflow etc;
494 * valid for Rx ports only */
496 /**< Number of Rx oversized frames, that is frames exceeding max frame
498 * valid for Rx ports only */
501 * Rx ports only */
510 * Rx and OP ports only */
513 * buffers due to DMA error; valid for Rx and O/H ports only */
524 /**< For Rx ports - Rx queue utilization, for Tx ports - Tx conf queue
529 /**< Number of cycles in which Rx pause activation control is on;
530 * valid for Rx ports only */
536 E_FMAN_PORT_DEQ_TOTAL, /**< DeQ tot frame cntr; invalid for Rx ports */
538 /**< Dequeue from default FQID counter not valid for Rx ports */
539 E_FMAN_PORT_DEQ_CONFIRM /**< DeQ confirm cntr invalid for Rx ports */