Lines Matching +full:0 +full:x0000003f
44 #define CMD_CFG_MG 0x80000000 /* 00 Magic Packet detection */
45 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */
46 #define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */
47 #define CMD_CFG_SFD_ANY 0x00200000 /* 10 Disable SFD check */
48 #define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */
49 #define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */
50 #define CMD_CFG_SEND_IDLE 0x00010000 /* 15 Force idle generation */
51 #define CMD_CFG_CNT_FRM_EN 0x00002000 /* 18 Control frame rx enable */
52 #define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */
53 #define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */
54 #define CMD_CFG_LOOPBACK_EN 0x00000400 /* 21 XGMII/GMII loopback enable */
55 #define CMD_CFG_TX_ADDR_INS 0x00000200 /* 22 Tx source MAC addr insertion */
56 #define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */
57 #define CMD_CFG_PAUSE_FWD 0x00000080 /* 24 Terminate/frwd Pause frames */
58 #define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */
59 #define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */
60 #define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */
61 #define CMD_CFG_WAN_MODE 0x00000008 /* 28 WAN mode enable */
62 #define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */
63 #define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */
66 #define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000
67 #define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF
68 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000
69 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000
70 #define TX_FIFO_SECTIONS_TX_EMPTY_PFC_10G 0x00360000
71 #define TX_FIFO_SECTIONS_TX_EMPTY_PFC_1G 0x00040000
72 #define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019
73 #define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020
74 #define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060
89 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
90 #define IF_MODE_XGMII 0x00000000 /* 30-31 XGMII (10G) interface */
91 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
92 #define IF_MODE_RGMII 0x00000004
93 #define IF_MODE_RGMII_AUTO 0x00008000
94 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
95 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
96 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
97 #define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */
98 #define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */
99 #define IF_MODE_HD 0x00000040 /* Half duplex operation */
103 #define HASH_CTRL_MCAST_EN 0x00000100 /* 23 Mcast frame rx for hash */
104 #define HASH_CTRL_ADDR_MASK 0x0000003F /* 26-31 Hash table address code */
106 #define GROUP_ADDRESS 0x0000010000000000LL /* MAC mcast indication */
110 #define MEMAC_TX_IPG_LENGTH_MASK 0x0000003F
113 #define STATS_CFG_CLR 0x00000004 /* 29 Reset all counters */
114 #define STATS_CFG_CLR_ON_RD 0x00000002 /* 30 Clear on read */
115 #define STATS_CFG_SATURATE 0x00000001 /* 31 Saturate at the maximum val */
118 #define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */
119 #define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */
120 #define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */
121 #define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */
129 #define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */
130 #define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */
131 #define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */
132 #define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */
133 #define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error */
134 #define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */
135 #define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
136 #define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */
137 #define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */
138 #define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */
139 #define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */
140 #define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */
141 #define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */
142 #define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */
143 #define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */
144 #define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */
145 #define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */
176 #define DEFAULT_PAUSE_QUANTA 0xf000
177 #define DEFAULT_FRAME_LENGTH 0x600
192 uint32_t command_config; /* 0x008 Ctrl and cfg */
193 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */
194 uint32_t maxfrm; /* 0x014 Max frame length */
199 uint32_t hashtable_ctrl; /* 0x02C Hash table control */
201 uint32_t ievent; /* 0x040 Interrupt event */
202 uint32_t tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */
204 uint32_t imask; /* 0x04C Interrupt mask */
206 uint32_t pause_quanta[4]; /* 0x054 Pause quanta */
207 uint32_t pause_thresh[4]; /* 0x064 Pause quanta threshold */
208 uint32_t rx_pause_status; /* 0x074 Receive pause status */
210 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS]; /* 0x80-0x0B4 mac padr */
211 uint32_t lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */
212 uint32_t sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */
214 uint32_t statn_config; /* 0x0E0 Statistics configuration */
316 uint32_t if_mode; /* 0x300 Interface Mode Control */
317 uint32_t if_status; /* 0x304 Interface Status */
320 uint32_t hg_config; /* 0x340 Control and cfg */
322 uint32_t hg_pause_quanta; /* 0x350 Pause quanta */
324 uint32_t hg_pause_thresh; /* 0x360 Pause quanta threshold */
326 uint32_t hgrx_pause_status; /* 0x370 Receive pause status */
327 uint32_t hg_fifos_status; /* 0x374 fifos status */
328 uint32_t rhm; /* 0x378 rx messages counter */
329 uint32_t thm; /* 0x37C tx messages counter */