Lines Matching +full:0 +full:x00000008
22 dcr-parent = <&{/cpus/cpu@0}>;
35 #size-cells = <0>;
37 cpu@0 {
40 reg = <0x00000000>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
54 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
60 cell-index = <0>;
61 dcr-reg = <0x0c0 0x009>;
62 #address-cells = <0>;
63 #size-cells = <0>;
71 dcr-reg = <0x0d0 0x009>;
72 #address-cells = <0>;
73 #size-cells = <0>;
75 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
83 dcr-reg = <0x0e0 0x009>;
84 #address-cells = <0>;
85 #size-cells = <0>;
87 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
93 dcr-reg = <0x00e 0x002>;
98 dcr-reg = <0x00c 0x002>;
106 clock-frequency = <0>; /* Filled in by zImage */
110 dcr-reg = <0x010 0x002>;
115 dcr-reg = <0x100 0x027>;
120 dcr-reg = <0x180 0x062>;
124 interrupts = <0x0 0x1 0x2 0x3 0x4>;
126 #address-cells = <0>;
127 #size-cells = <0>;
128 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
129 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
130 /*SERR*/ 0x2 &UIC1 0x0 0x4
131 /*TXDE*/ 0x3 &UIC1 0x1 0x4
132 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
133 interrupt-map-mask = <0xffffffff>;
140 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
141 0x80000000 0x00000001 0x80000000 0x80000000>;
143 interrupts = <0x7 0x4>;
144 clock-frequency = <0>; /* Filled in by zImage */
148 dcr-reg = <0x012 0x002>;
151 clock-frequency = <0>; /* Filled in by zImage */
152 interrupts = <0x5 0x1>;
155 nor_flash@0,0 {
158 reg = <0x00000000 0x00000000 0x04000000>;
161 partition@0 {
163 reg = <0x00000000 0x00180000>;
167 reg = <0x00180000 0x00200000>;
171 reg = <0x00380000 0x03aa0000>;
175 reg = <0x03e20000 0x00140000>;
179 reg = <0x03f60000 0x00040000>;
183 reg = <0x03fa0000 0x00060000>;
192 reg = <0xef600300 0x00000008>;
193 virtual-reg = <0xef600300>;
194 clock-frequency = <0>; /* Filled in by zImage */
197 interrupts = <0x0 0x4>;
203 reg = <0xef600400 0x00000008>;
204 virtual-reg = <0xef600400>;
205 clock-frequency = <0>;
206 current-speed = <0>;
208 interrupts = <0x1 0x4>;
214 reg = <0xef600500 0x00000008>;
215 virtual-reg = <0xef600500>;
216 clock-frequency = <0>;
217 current-speed = <0>;
219 interrupts = <0x3 0x4>;
225 reg = <0xef600600 0x00000008>;
226 virtual-reg = <0xef600600>;
227 clock-frequency = <0>;
228 current-speed = <0>;
230 interrupts = <0x4 0x4>;
235 reg = <0xef600700 0x00000014>;
237 interrupts = <0x2 0x4>;
242 reg = <0xef600800 0x00000014>;
244 interrupts = <0x7 0x4>;
249 reg = <0xef600d00 0x0000000c>;
254 reg = <0xef601000 0x00000008>;
262 interrupts = <0x0 0x1>;
264 #address-cells = <0>;
265 #size-cells = <0>;
266 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
267 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
268 reg = <0xef600e00 0x00000074>;
271 mal-tx-channel = <0>;
272 mal-rx-channel = <0>;
273 cell-index = <0>;
278 phy-map = <0x00000000>;
280 zmii-channel = <0>;
282 rgmii-channel = <0>;
291 interrupts = <0x0 0x1>;
293 #address-cells = <0>;
294 #size-cells = <0>;
295 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
296 /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
297 reg = <0xef600f00 0x00000074>;
307 phy-map = <0x00000000>;
324 reg = <0x00000001 0xeec00000 0x00000008 /* Config space access */
325 0x00000001 0xeed00000 0x00000004 /* IACK */
326 0x00000001 0xeed00000 0x00000004 /* Special cycle */
327 0x00000001 0xef400000 0x00000040>; /* Internal registers */
333 ranges = <0x02000000 0x0 0x80000000 0x1 0x80000000 0x0 0x40000000
334 0x01000000 0x0 0x00000000 0x1 0xe8000000 0x0 0x00010000
335 0x01000000 0x0 0x00000000 0x1 0xe8800000 0x0 0x03800000>;
337 /* Inbound 2GB range starting at 0 */
338 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
341 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
342 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC2 0x3 0x8 >;