Lines Matching defs:gcc
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
469 gcc: clock-controller@80000 {
470 compatible = "qcom,sdx75-gcc";
526 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
527 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
542 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
565 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
588 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
607 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
630 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
653 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
676 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
699 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
715 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
738 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
761 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
784 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
807 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
836 resets = <&gcc GCC_QUSB2PHY_BCR>;
845 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
846 <&gcc GCC_USB2_CLKREF_EN>,
847 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
848 <&gcc GCC_USB3_PHY_PIPE_CLK>;
854 power-domains = <&gcc GCC_USB3_PHY_GDSC>;
856 resets = <&gcc GCC_USB3_PHY_BCR>,
857 <&gcc GCC_USB3PHY_PHY_BCR>;
950 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
951 <&gcc GCC_SDCC1_APPS_CLK>,
996 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
997 <&gcc GCC_USB30_MASTER_CLK>,
998 <&gcc GCC_USB30_MSTR_AXI_CLK>,
999 <&gcc GCC_USB30_SLEEP_CLK>,
1000 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
1007 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1008 <&gcc GCC_USB30_MASTER_CLK>;
1020 power-domains = <&gcc GCC_USB30_GDSC>;
1022 resets = <&gcc GCC_USB30_BCR>;
1522 <&gcc GPLL0>;