Lines Matching defs:gcc
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
600 gcc: clock-controller@100000 {
601 compatible = "qcom,gcc-sdm670";
637 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
638 <&gcc GCC_SDCC1_APPS_CLK>,
640 <&gcc GCC_SDCC1_ICE_CORE_CLK>,
641 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
720 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
721 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
734 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
755 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
776 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
797 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
818 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
839 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
860 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
881 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
926 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
927 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
940 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
961 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
982 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1003 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1024 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1045 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1066 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1087 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1307 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1311 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1326 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1327 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1328 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1329 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1330 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1337 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1338 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1352 power-domains = <&gcc USB30_PRIM_GDSC>;
1354 resets = <&gcc GCC_USB30_PRIM_BCR>;
1437 clocks = <&gcc GCC_DISP_AXI_CLK>,
1442 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
1648 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
1649 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
1842 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1853 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;