Lines Matching full:gcc
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
799 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
800 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
801 <&gcc GCC_EMAC0_PTP_CLK>,
802 <&gcc GCC_EMAC0_RGMII_CLK>;
813 power-domains = <&gcc EMAC_0_GDSC>;
823 gcc: clock-controller@100000 {
824 compatible = "qcom,gcc-sc8280xp";
889 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
890 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
905 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
921 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
937 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
953 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
967 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
983 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
999 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1015 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1031 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1047 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1063 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1078 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1095 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1112 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1127 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1144 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1159 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1174 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1175 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1191 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1206 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1223 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1238 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1255 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1270 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1284 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1301 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1316 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1331 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1348 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1365 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1380 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1397 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1412 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1429 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1444 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1459 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1460 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1475 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1491 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1507 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1523 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1539 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1555 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1571 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1587 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1603 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1619 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1635 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1651 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1667 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1683 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1699 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1715 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1770 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1771 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1772 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
1773 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
1774 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
1775 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1776 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1777 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
1778 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
1789 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1796 resets = <&gcc GCC_PCIE_4_BCR>;
1799 power-domains = <&gcc PCIE_4_GDSC>;
1822 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1823 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1824 <&gcc GCC_PCIE_4_CLKREF_CLK>,
1825 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
1826 <&gcc GCC_PCIE_4_PIPE_CLK>,
1827 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
1831 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1834 power-domains = <&gcc PCIE_4_GDSC>;
1836 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
1883 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1884 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1885 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1886 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1887 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1888 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1889 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1890 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1900 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1907 resets = <&gcc GCC_PCIE_3B_BCR>;
1910 power-domains = <&gcc PCIE_3B_GDSC>;
1933 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1934 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1935 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1936 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1937 <&gcc GCC_PCIE_3B_PIPE_CLK>,
1938 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1942 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1945 power-domains = <&gcc PCIE_3B_GDSC>;
1947 resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1994 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1995 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1996 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1997 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1998 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1999 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2000 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2001 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2011 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
2018 resets = <&gcc GCC_PCIE_3A_BCR>;
2021 power-domains = <&gcc PCIE_3A_GDSC>;
2045 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
2046 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
2047 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
2048 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
2049 <&gcc GCC_PCIE_3A_PIPE_CLK>,
2050 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
2054 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
2057 power-domains = <&gcc PCIE_3A_GDSC>;
2059 resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2108 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2109 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2110 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2111 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2112 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2113 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2114 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2115 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2125 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2132 resets = <&gcc GCC_PCIE_2B_BCR>;
2135 power-domains = <&gcc PCIE_2B_GDSC>;
2158 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2159 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2160 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2161 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2162 <&gcc GCC_PCIE_2B_PIPE_CLK>,
2163 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2167 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2170 power-domains = <&gcc PCIE_2B_GDSC>;
2172 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2219 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2220 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2221 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2222 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2223 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2224 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2225 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2226 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2236 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2243 resets = <&gcc GCC_PCIE_2A_BCR>;
2246 power-domains = <&gcc PCIE_2A_GDSC>;
2270 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2271 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2272 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2273 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2274 <&gcc GCC_PCIE_2A_PIPE_CLK>,
2275 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2279 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2282 power-domains = <&gcc PCIE_2A_GDSC>;
2284 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2306 resets = <&gcc GCC_UFS_PHY_BCR>;
2309 power-domains = <&gcc UFS_PHY_GDSC>;
2315 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2316 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2317 <&gcc GCC_UFS_PHY_AHB_CLK>,
2318 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2319 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2320 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2321 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2322 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2347 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2348 <&gcc GCC_UFS_CARD_CLKREF_CLK>;
2353 power-domains = <&gcc UFS_PHY_GDSC>;
2372 resets = <&gcc GCC_UFS_CARD_BCR>;
2375 power-domains = <&gcc UFS_CARD_GDSC>;
2380 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2381 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2382 <&gcc GCC_UFS_CARD_AHB_CLK>,
2383 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2384 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2385 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2386 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2387 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2412 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
2413 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>;
2418 power-domains = <&gcc UFS_CARD_GDSC>;
2523 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2524 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2561 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2562 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2594 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2595 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2619 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2630 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
2632 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
2643 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
2645 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
2656 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
2658 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
2669 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
2671 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
2682 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2683 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
2684 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2685 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2688 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2689 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2692 power-domains = <&gcc USB30_MP_GDSC>;
2706 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2707 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
2708 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2709 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2712 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2713 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2716 power-domains = <&gcc USB30_MP_GDSC>;
3159 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3160 <&gcc GCC_SDCC2_APPS_CLK>,
3163 resets = <&gcc GCC_SDCC2_BCR>;
3198 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3199 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3200 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3201 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3204 power-domains = <&gcc USB30_PRIM_GDSC>;
3206 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3207 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3250 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3259 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3260 <&gcc GCC_USB4_CLKREF_CLK>,
3261 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3262 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3265 power-domains = <&gcc USB30_SEC_GDSC>;
3267 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3268 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3449 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
3450 <&gcc GCC_USB30_MP_MASTER_CLK>,
3451 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
3452 <&gcc GCC_USB30_MP_SLEEP_CLK>,
3453 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3454 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3455 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3456 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3457 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3461 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
3462 <&gcc GCC_USB30_MP_MASTER_CLK>;
3494 power-domains = <&gcc USB30_MP_GDSC>;
3497 resets = <&gcc GCC_USB30_MP_BCR>;
3531 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3532 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3533 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3534 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3535 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3536 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3537 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3538 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3539 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3543 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3544 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3558 power-domains = <&gcc USB30_PRIM_GDSC>;
3561 resets = <&gcc GCC_USB30_PRIM_BCR>;
3608 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3609 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3610 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3611 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3612 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3613 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3614 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3615 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3616 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3620 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3621 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3635 power-domains = <&gcc USB30_SEC_GDSC>;
3638 resets = <&gcc GCC_USB30_SEC_BCR>;
3975 <&gcc GCC_CAMERA_HF_AXI_CLK>,
3976 <&gcc GCC_CAMERA_SF_AXI_CLK>;
4079 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4095 clocks = <&gcc GCC_DISP_AHB_CLK>,
4123 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4124 <&gcc GCC_DISP_SF_AXI_CLK>,
4547 clocks = <&gcc GCC_DISP_AHB_CLK>,
5182 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5199 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5381 clocks = <&gcc GCC_DISP_AHB_CLK>,
5410 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5411 <&gcc GCC_DISP_SF_AXI_CLK>,
5821 clocks = <&gcc GCC_DISP_AHB_CLK>,
5851 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
5852 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
5853 <&gcc GCC_EMAC1_PTP_CLK>,
5854 <&gcc GCC_EMAC1_RGMII_CLK>;
5865 power-domains = <&gcc EMAC_1_GDSC>;