Lines Matching defs:gcc
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
651 gcc: clock-controller@1400000 {
652 compatible = "qcom,gcc-qcm2290";
665 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
669 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
680 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
681 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
682 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
683 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
689 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
690 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
899 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
900 <&gcc GCC_SDCC1_APPS_CLK>,
902 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
908 resets = <&gcc GCC_SDCC1_BCR>;
961 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
962 <&gcc GCC_SDCC2_APPS_CLK>,
968 resets = <&gcc GCC_SDCC2_BCR>;
1028 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1029 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1041 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1066 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1088 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1105 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1130 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1152 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1177 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1199 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1224 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1246 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1272 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1293 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1310 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1335 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1362 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1363 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1364 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1365 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1366 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1367 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1375 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1376 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1379 resets = <&gcc GCC_USB30_PRIM_BCR>;
1380 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1443 <&gcc GCC_BIMC_GPU_AXI_CLK>,
1444 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1544 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1546 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1547 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1569 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1571 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1590 clocks = <&gcc GCC_DISP_AHB_CLK>,
1591 <&gcc GCC_DISP_HF_AXI_CLK>,
1626 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1695 <&gcc GCC_DISP_HF_AXI_CLK>;
1786 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
1787 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
2059 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;