Lines Matching +full:1 +full:hz
45 opp-hz = /bits/ 64 <500000000>;
50 opp-hz = /bits/ 64 <560000000>;
55 opp-hz = /bits/ 64 <612000000>;
60 opp-hz = /bits/ 64 <682000000>;
65 opp-hz = /bits/ 64 <752000000>;
70 opp-hz = /bits/ 64 <822000000>;
75 opp-hz = /bits/ 64 <875000000>;
80 opp-hz = /bits/ 64 <927000000>;
85 opp-hz = /bits/ 64 <980000000>;
90 opp-hz = /bits/ 64 <1050000000>;
95 opp-hz = /bits/ 64 <1120000000>;
100 opp-hz = /bits/ 64 <1155000000>;
105 opp-hz = /bits/ 64 <1190000000>;
110 opp-hz = /bits/ 64 <1260000000>;
115 opp-hz = /bits/ 64 <1330000000>;
120 opp-hz = /bits/ 64 <1400000000>;
130 opp-hz = /bits/ 64 <500000000>;
136 opp-hz = /bits/ 64 <774000000>;
142 opp-hz = /bits/ 64 <875000000>;
148 opp-hz = /bits/ 64 <975000000>;
154 opp-hz = /bits/ 64 <1075000000>;
160 opp-hz = /bits/ 64 <1175000000>;
166 opp-hz = /bits/ 64 <1275000000>;
172 opp-hz = /bits/ 64 <1375000000>;
178 opp-hz = /bits/ 64 <1500000000>;
184 opp-hz = /bits/ 64 <1618000000>;
190 opp-hz = /bits/ 64 <1666000000>;
196 opp-hz = /bits/ 64 <1733000000>;
202 opp-hz = /bits/ 64 <1800000000>;
208 opp-hz = /bits/ 64 <1866000000>;
214 opp-hz = /bits/ 64 <1933000000>;
220 opp-hz = /bits/ 64 <2000000000>;
231 opp-hz = /bits/ 64 <774000000>;
237 opp-hz = /bits/ 64 <835000000>;
243 opp-hz = /bits/ 64 <919000000>;
249 opp-hz = /bits/ 64 <1002000000>;
255 opp-hz = /bits/ 64 <1085000000>;
261 opp-hz = /bits/ 64 <1169000000>;
267 opp-hz = /bits/ 64 <1308000000>;
273 opp-hz = /bits/ 64 <1419000000>;
279 opp-hz = /bits/ 64 <1530000000>;
285 opp-hz = /bits/ 64 <1670000000>;
291 opp-hz = /bits/ 64 <1733000000>;
297 opp-hz = /bits/ 64 <1796000000>;
303 opp-hz = /bits/ 64 <1860000000>;
309 opp-hz = /bits/ 64 <1923000000>;
315 opp-hz = /bits/ 64 <1986000000>;
321 opp-hz = /bits/ 64 <2050000000>;
328 #address-cells = <1>;
634 clock-mult = <1>;
656 opp-hz = /bits/ 64 <299000000>;
662 opp-hz = /bits/ 64 <332000000>;
668 opp-hz = /bits/ 64 <366000000>;
674 opp-hz = /bits/ 64 <400000000>;
680 opp-hz = /bits/ 64 <434000000>;
686 opp-hz = /bits/ 64 <484000000>;
692 opp-hz = /bits/ 64 <535000000>;
698 opp-hz = /bits/ 64 <586000000>;
704 opp-hz = /bits/ 64 <637000000>;
710 opp-hz = /bits/ 64 <690000000>;
716 opp-hz = /bits/ 64 <743000000>;
722 opp-hz = /bits/ 64 <796000000>;
728 opp-hz = /bits/ 64 <850000000>;
734 opp-hz = /bits/ 64 <900000000>;
740 opp-hz = /bits/ 64 <900000000>;
746 opp-hz = /bits/ 64 <900000000>;
752 opp-hz = /bits/ 64 <950000000>;
758 opp-hz = /bits/ 64 <950000000>;
764 opp-hz = /bits/ 64 <950000000>;
770 opp-hz = /bits/ 64 <1000000000>;
776 opp-hz = /bits/ 64 <1000000000>;
782 opp-hz = /bits/ 64 <1000000000>;
824 #redistributor-regions = <1>;
836 ppi_cluster1: interrupt-partition-1 {
845 #clock-cells = <1>;
851 #clock-cells = <1>;
857 #clock-cells = <1>;
858 #reset-cells = <1>;
893 #address-cells = <1>;
895 #power-domain-cells = <1>;
902 #address-cells = <1>;
904 #power-domain-cells = <1>;
909 #address-cells = <1>;
911 #power-domain-cells = <1>;
956 #address-cells = <1>;
958 #power-domain-cells = <1>;
962 #address-cells = <1>;
964 #power-domain-cells = <1>;
994 #address-cells = <1>;
996 #power-domain-cells = <1>;
1021 #address-cells = <1>;
1023 #power-domain-cells = <1>;
1042 #address-cells = <1>;
1044 #power-domain-cells = <1>;
1096 #reset-cells = <1>;
1102 #clock-cells = <1>;
1202 #io-channel-cells = <1>;
1235 clock-div = <1>;
1236 #address-cells = <1>;
1249 clock-div = <1>;
1250 #address-cells = <1>;
1263 clock-div = <1>;
1264 #address-cells = <1>;
1277 clock-div = <1>;
1278 #address-cells = <1>;
1291 clock-div = <1>;
1292 #address-cells = <1>;
1305 clock-div = <1>;
1306 #address-cells = <1>;
1319 clock-div = <1>;
1320 #address-cells = <1>;
1333 clock-div = <1>;
1334 #address-cells = <1>;
1347 clock-div = <1>;
1348 #address-cells = <1>;
1355 #address-cells = <1>;
1373 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1374 #thermal-sensor-cells = <1>;
1402 #address-cells = <1>;
1415 #address-cells = <1>;
1428 #address-cells = <1>;
1441 #address-cells = <1>;
1454 #address-cells = <1>;
1468 #clock-cells = <1>;
1489 clock-div = <1>;
1490 #address-cells = <1>;
1661 #address-cells = <1>;
1662 #size-cells = <1>;
1670 #phy-cells = <1>;
1677 #phy-cells = <1>;
1684 #address-cells = <1>;
1685 #size-cells = <1>;
1693 #phy-cells = <1>;
1701 #address-cells = <1>;
1702 #size-cells = <1>;
1704 lvts_efuse_data1: lvts1-calib@1cc {
1739 #clock-cells = <1>;
1766 #clock-cells = <1>;
1767 #reset-cells = <1>;
1769 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1810 mediatek,larb-id = <1>;
1948 #iommu-cells = <1>;
1964 #clock-cells = <1>;
1981 #clock-cells = <1>;
1998 #clock-cells = <1>;
2063 #clock-cells = <1>;
2069 #clock-cells = <1>;
2117 camsys: clock-controller@1a000000 {
2120 #clock-cells = <1>;
2123 larb13: smi@1a001000 {
2133 larb14: smi@1a002000 {
2143 larb16: smi@1a00f000 {
2154 larb17: smi@1a010000 {
2165 camsys_rawa: clock-controller@1a04f000 {
2168 #clock-cells = <1>;
2171 camsys_rawb: clock-controller@1a06f000 {
2174 #clock-cells = <1>;
2177 mdpsys: clock-controller@1b000000 {
2180 #clock-cells = <1>;
2183 larb2: smi@1b002000 {
2193 ipesys: clock-controller@1c000000 {
2196 #clock-cells = <1>;
2199 larb20: smi@1c00f000 {
2209 larb19: smi@1c10f000 {