Lines Matching defs:gcc
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
204 gcc: clock-controller@100000 {
205 compatible = "qcom,gcc-sdx65";
226 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
238 resets = <&gcc GCC_QUSB2PHY_BCR>;
246 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
247 <&gcc GCC_USB3_PRIM_CLKREF_EN>,
248 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
249 <&gcc GCC_USB3_PHY_PIPE_CLK>;
258 resets = <&gcc GCC_USB3_PHY_BCR>,
259 <&gcc GCC_USB3PHY_PHY_BCR>;
319 clocks = <&gcc GCC_PCIE_AUX_CLK>,
320 <&gcc GCC_PCIE_CFG_AHB_CLK>,
321 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
322 <&gcc GCC_PCIE_SLV_AXI_CLK>,
323 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
324 <&gcc GCC_PCIE_SLEEP_CLK>,
325 <&gcc GCC_PCIE_0_CLKREF_EN>;
338 resets = <&gcc GCC_PCIE_BCR>;
341 power-domains = <&gcc PCIE_GDSC>;
356 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
357 <&gcc GCC_PCIE_CFG_AHB_CLK>,
358 <&gcc GCC_PCIE_0_CLKREF_EN>,
359 <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
360 <&gcc GCC_PCIE_PIPE_CLK>;
367 resets = <&gcc GCC_PCIE_PHY_BCR>;
370 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
373 power-domains = <&gcc PCIE_GDSC>;
472 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
473 <&gcc GCC_SDCC1_APPS_CLK>;
492 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
493 <&gcc GCC_USB30_MASTER_CLK>,
494 <&gcc GCC_USB30_MSTR_AXI_CLK>,
495 <&gcc GCC_USB30_SLEEP_CLK>,
496 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
500 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
501 <&gcc GCC_USB30_MASTER_CLK>;
515 power-domains = <&gcc USB30_GDSC>;
517 resets = <&gcc GCC_USB30_BCR>;
648 compatible = "qcom,sdx55-apcs-gcc", "syscon";
651 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;