Lines Matching defs:gcc
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
335 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
344 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
353 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
362 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
418 clocks = <&gcc GSBI1_H_CLK>;
431 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
443 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
457 clocks = <&gcc GSBI2_H_CLK>;
472 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
485 clocks = <&gcc GSBI3_H_CLK>;
497 clocks = <&gcc GSBI3_QUP_CLK>,
498 <&gcc GSBI3_H_CLK>;
511 clocks = <&gcc GSBI4_H_CLK>;
524 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
536 clocks = <&gcc GSBI4_QUP_CLK>,
537 <&gcc GSBI4_H_CLK>;
548 clocks = <&gcc GSBI5_H_CLK>;
559 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
571 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
584 clocks = <&gcc GSBI6_H_CLK>;
595 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
607 clocks = <&gcc GSBI6_QUP_CLK>,
608 <&gcc GSBI6_H_CLK>;
619 clocks = <&gcc GSBI7_H_CLK>;
631 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
643 clocks = <&gcc GSBI7_QUP_CLK>,
644 <&gcc GSBI7_H_CLK>;
653 clocks = <&gcc PRNG_CLK>;
683 gcc: clock-controller@900000 {
684 compatible = "qcom,gcc-apq8064", "syscon";
712 <&gcc PLL4_VOTE>,
734 <&gcc PLL3>,
735 <&gcc PLL8_VOTE>,
752 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
754 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
782 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
784 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
786 resets = <&gcc USB_HS1_RESET>;
813 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
815 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
817 resets = <&gcc USB_HS3_RESET>;
844 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
846 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
848 resets = <&gcc USB_HS4_RESET>;
874 clocks = <&gcc SATA_PHY_CFG_CLK>;
885 clocks = <&gcc SFAB_SATA_S_H_CLK>,
886 <&gcc SATA_H_CLK>,
887 <&gcc SATA_A_CLK>,
888 <&gcc SATA_RXOOB_CLK>,
889 <&gcc SATA_PMALIVE_CLK>;
896 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
897 <&gcc SATA_PMALIVE_CLK>;
911 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
926 clocks = <&gcc SDC3_H_CLK>;
938 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
954 clocks = <&gcc SDC4_H_CLK>;
968 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
983 clocks = <&gcc SDC1_H_CLK>;
1324 clocks = <&gcc PCIE_A_CLK>,
1325 <&gcc PCIE_H_CLK>,
1326 <&gcc PCIE_PHY_REF_CLK>;
1328 resets = <&gcc PCIE_ACLK_RESET>,
1329 <&gcc PCIE_HCLK_RESET>,
1330 <&gcc PCIE_POR_RESET>,
1331 <&gcc PCIE_PCI_RESET>,
1332 <&gcc PCIE_PHY_RESET>;