Lines Matching full:clks
76 clocks = <&clks IMX7D_USB_PHY2_CLK>;
93 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
141 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
142 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
143 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
145 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
146 <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
147 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
148 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
174 clocks = <&clks IMX7D_PXP_CLK>;
184 clocks = <&clks IMX7D_USB_CTRL_CLK>;
205 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
206 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
207 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
208 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
209 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;