Lines Matching +full:zynqmp +full:- +full:reset
4 - compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
5 - reg: Base address and length of the register control block
6 - clocks: A list of phandles for the clocks listed in clock-names
7 - clock-names: Should contain the following:
12 - resets: A list of phandles for resets listed in reset-names
13 - reset-names:
14 "usb_crst" USB core reset
15 "usb_hibrst" USB hibernation reset
16 "usb_apbrst" USB APB reset
23 - dma-coherent: Enable this flag if CCI is enabled in design. Adding this
25 Xilinx USB 3.0 IP - USB coherency register to enable CCI.
26 - interrupt-names: Should contain the following:
34 #address-cells = <0x2>;
35 #size-cells = <0x1>;
36 compatible = "xlnx,zynqmp-dwc3";
38 clock-names = "bus_clk", "ref_clk";
43 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
49 interrupt-names = "dwc_usb3", "otg", "hiber";
52 phy-names = "usb3-phy";
54 dma-coherent;