Lines Matching +full:spi +full:- +full:mux

1 Binding for MTK SPI Slave controller
4 - compatible: should be one of the following.
5     - mediatek,mt2712-spi-slave: for mt2712 platforms
6     - mediatek,mt8195-spi-slave: for mt8195 platforms
7 - reg: Address and length of the register set for the device.
8 - interrupts: Should contain spi interrupt.
9 - clocks: phandles to input clocks.
11 - clock-names: should be "spi" for the clock gate.
14 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
15 - assigned-clock-parents: parent of mux clock.
17    -  <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
19    -  <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
20    -  <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
21    -  <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
24 - SoC Specific Portion:
25 spis1: spi@10013000 {
26 	compatible = "mediatek,mt2712-spi-slave";
30 	clock-names = "spi";
31 	assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
32 	assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;