Lines Matching +full:mt2701 +full:- +full:larb +full:- +full:port
7 generation 1: mt2701 and mt7623.
11 register which control the iommu port is at each larb's register base. But
18 - compatible : must be one of :
19 "mediatek,mt2701-smi-common"
20 "mediatek,mt2712-smi-common"
21 "mediatek,mt6779-smi-common"
22 "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
23 "mediatek,mt8167-smi-common"
24 "mediatek,mt8173-smi-common"
25 "mediatek,mt8183-smi-common"
26 - reg : the register and size of the SMI block.
27 - power-domains : a phandle to the power domain of this local arbiter.
28 - clocks : Must contain an entry for each entry in clock-names.
29 - clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
31 - "apb" : Advanced Peripheral Bus clock, It's the clock for setting
33 - "smi" : It's the clock for transfer data and command.
35 - "async" : asynchronous clock, it help transform the smi clock into the emi
38 - "gals0": the path0 clock of GALS(Global Async Local Sync).
39 - "gals1": the path1 clock of GALS(Global Async Local Sync).
44 compatible = "mediatek,mt8173-smi-common";
46 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
49 clock-names = "apb", "smi";