Lines Matching +full:test +full:- +full:part1
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
281 rtwdev->dbcc_en, phy_idx);
283 if (!rtwdev->dbcc_en) {
310 RTW8852B_RXDCK_VER, rtwdev->hal.cv);
316 if (rtwdev->is_tssi_mode[path])
328 if (rtwdev->is_tssi_mode[path])
405 struct rtw89_dack_info *dack = &rtwdev->dack;
408 dack->addck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A0);
409 dack->addck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A1);
412 dack->addck_d[1][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1, B_ADDCKR1_A0);
413 dack->addck_d[1][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR1, B_ADDCKR1_A1);
418 struct rtw89_dack_info *dack = &rtwdev->dack;
421 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK0D_VAL, dack->addck_d[0][0]);
422 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_VAL, dack->addck_d[0][1] >> 6);
423 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK0D_VAL2, dack->addck_d[0][1] & 0x3f);
427 rtw89_phy_write32_mask(rtwdev, R_ADDCK1D, B_ADDCK1D_VAL, dack->addck_d[1][0]);
428 rtw89_phy_write32_mask(rtwdev, R_ADDCK1, B_ADDCK0_VAL, dack->addck_d[1][1] >> 6);
429 rtw89_phy_write32_mask(rtwdev, R_ADDCK1D, B_ADDCK1D_VAL2, dack->addck_d[1][1] & 0x3f);
435 struct rtw89_dack_info *dack = &rtwdev->dack;
442 dack->msbk_d[0][0][i] =
445 dack->msbk_d[0][1][i] =
449 dack->biask_d[0][0] =
451 dack->biask_d[0][1] =
454 dack->dadck_d[0][0] =
456 dack->dadck_d[0][1] =
462 struct rtw89_dack_info *dack = &rtwdev->dack;
469 dack->msbk_d[1][0][i] =
472 dack->msbk_d[1][1][i] =
476 dack->biask_d[1][0] =
478 dack->biask_d[1][1] =
481 dack->dadck_d[1][0] =
483 dack->dadck_d[1][1] =
512 struct rtw89_dack_info *dack = &rtwdev->dack;
540 dack->addck_timeout[0] = true;
574 dack->addck_timeout[1] = true;
600 static bool _dack_s0_check_done(struct rtw89_dev *rtwdev, bool part1)
602 if (part1) {
617 struct rtw89_dack_info *dack = &rtwdev->dack;
627 dack->msbk_timeout[0] = true;
637 dack->dadck_timeout[0] = true;
649 static bool _dack_s1_check_done(struct rtw89_dev *rtwdev, bool part1)
651 if (part1) {
666 struct rtw89_dack_info *dack = &rtwdev->dack;
676 dack->msbk_timeout[1] = true;
686 dack->dadck_timeout[1] = true;
707 struct rtw89_dack_info *dack = &rtwdev->dack;
713 dack->addck_d[0][0], dack->addck_d[0][1]);
716 dack->addck_d[1][0], dack->addck_d[1][1]);
719 dack->dadck_d[0][0], dack->dadck_d[0][1]);
722 dack->dadck_d[1][0], dack->dadck_d[1][1]);
725 dack->biask_d[0][0], dack->biask_d[0][1]);
728 dack->biask_d[1][0], dack->biask_d[1][1]);
732 t = dack->msbk_d[0][0][i];
738 t = dack->msbk_d[0][1][i];
744 t = dack->msbk_d[1][0][i];
750 t = dack->msbk_d[1][1][i];
757 struct rtw89_dack_info *dack = &rtwdev->dack;
760 dack->dack_done = false;
781 dack->dack_done = true;
787 dack->dack_cnt++;
793 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
796 switch (iqk_info->iqk_band[path]) {
817 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
837 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
845 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8);
872 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
878 switch (iqk_info->iqk_band[path]) {
913 iqk_info->nb_rxcfir[path] = 0x40000002;
916 iqk_info->is_wb_rxiqk[path] = false;
918 iqk_info->nb_rxcfir[path] = 0x40000000;
921 iqk_info->is_wb_rxiqk[path] = true;
930 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
935 switch (iqk_info->iqk_band[path]) {
968 iqk_info->nb_rxcfir[path] =
971 iqk_info->nb_rxcfir[path] = 0x40000002;
978 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
980 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) {
1017 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1023 switch (iqk_info->iqk_band[path]) {
1064 iqk_info->nb_txcfir[path] = 0x40000002;
1067 iqk_info->is_wb_txiqk[path] = false;
1069 iqk_info->nb_txcfir[path] = 0x40000000;
1072 iqk_info->is_wb_txiqk[path] = true;
1080 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1084 switch (iqk_info->iqk_band[path]) {
1117 iqk_info->nb_txcfir[path] =
1121 iqk_info->nb_txcfir[path] = 0x40000002;
1128 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1134 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1148 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1160 ch = (iqk_info->iqk_times / 2) % RTW89_IQK_CHS_NR;
1167 iqk_info->lok_idac[ch][path] = tmp;
1178 iqk_info->lok_vbuf[ch][path] = tmp;
1182 iqk_info->lok_idac[ch][path]);
1185 iqk_info->lok_vbuf[ch][path]);
1192 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1197 switch (iqk_info->iqk_band[path]) {
1210 switch (iqk_info->iqk_band[path]) {
1223 iqk_info->lok_cor_fail[0][path] = tmp;
1225 switch (iqk_info->iqk_band[path]) {
1239 switch (iqk_info->iqk_band[path]) {
1253 iqk_info->lok_fin_fail[0][path] = tmp;
1255 switch (iqk_info->iqk_band[path]) {
1274 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1276 switch (iqk_info->iqk_band[path]) {
1317 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1321 flag = iqk_info->lok_cor_fail[0][path];
1323 flag = iqk_info->lok_fin_fail[0][path];
1325 flag = iqk_info->iqk_tx_fail[0][path];
1327 flag = iqk_info->iqk_rx_fail[0][path];
1331 iqk_info->bp_iqkenable[path] = tmp;
1333 iqk_info->bp_txkresult[path] = tmp;
1335 iqk_info->bp_rxkresult[path] = tmp;
1337 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, B_IQKINF2_KCNT, iqk_info->iqk_times);
1341 iqk_info->iqk_fail_cnt++;
1343 iqk_info->iqk_fail_cnt);
1348 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1369 if (iqk_info->is_nbiqk)
1370 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path);
1372 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path);
1377 if (iqk_info->is_nbiqk)
1378 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path);
1380 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path);
1388 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1395 if (iqk_info->iqk_mcc_ch[idx][path] == 0) {
1403 idx = iqk_info->iqk_table_idx[path] + 1;
1412 iqk_info->iqk_band[path] = chan->band_type;
1413 iqk_info->iqk_bw[path] = chan->band_width;
1414 iqk_info->iqk_ch[path] = chan->channel;
1415 iqk_info->iqk_mcc_ch[idx][path] = chan->channel;
1416 iqk_info->iqk_table_idx[path] = idx;
1423 iqk_info->iqk_times, idx);
1425 idx, path, iqk_info->iqk_mcc_ch[idx][path]);
1428 iqk_info->syn1to2 = 0x1;
1430 iqk_info->syn1to2 = 0x0;
1433 "[IQK]S%x, iqk_info->syn1to2= 0x%x\n", path,
1434 iqk_info->syn1to2);
1439 iqk_info->iqk_band[path]);
1442 iqk_info->iqk_bw[path]);
1444 iqk_info->iqk_ch[path]);
1454 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1458 iqk_info->nb_txcfir[path]);
1460 iqk_info->nb_rxcfir[path]);
1503 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
1508 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1511 idx = iqk_info->iqk_table_idx[path];
1549 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
1554 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1558 if (iqk_info->is_iqk_init)
1562 iqk_info->is_iqk_init = true;
1563 iqk_info->is_nbiqk = false;
1564 iqk_info->iqk_fft_en = false;
1565 iqk_info->iqk_sram_en = false;
1566 iqk_info->iqk_cfir_en = false;
1567 iqk_info->iqk_xym_en = false;
1568 iqk_info->iqk_times = 0x0;
1571 iqk_info->iqk_channel[idx] = 0x0;
1573 iqk_info->lok_cor_fail[idx][path] = false;
1574 iqk_info->lok_fin_fail[idx][path] = false;
1575 iqk_info->iqk_tx_fail[idx][path] = false;
1576 iqk_info->iqk_rx_fail[idx][path] = false;
1577 iqk_info->iqk_mcc_ch[idx][path] = 0x0;
1578 iqk_info->iqk_table_idx[path] = 0x0;
1613 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1622 iqk_info->iqk_times++;
1623 iqk_info->version = RTW8852B_IQK_VER;
1625 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
1702 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1703 u8 val, kidx = dpk->cur_idx[path];
1705 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok;
1711 kidx, dpk->is_dpk_enable && !off ? "enable" : "disable");
1728 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot over 20ms!!!!\n");
1738 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot over 20ms!!!!\n");
1743 "[DPK] one-shot for %s = 0x%x\n",
1767 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1769 u8 kidx = dpk->cur_idx[path];
1771 dpk->bp[path][kidx].band = chan->band_type;
1772 dpk->bp[path][kidx].ch = chan->channel;
1773 dpk->bp[path][kidx].bw = chan->band_width;
1777 path, dpk->cur_idx[path], phy,
1778 rtwdev->is_tssi_mode[path] ? "on" : "off",
1779 rtwdev->dbcc_en ? "on" : "off",
1780 dpk->bp[path][kidx].band == 0 ? "2G" :
1781 dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1782 dpk->bp[path][kidx].ch,
1783 dpk->bp[path][kidx].bw == 0 ? "20M" :
1784 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M");
1795 if (chan->band_width == RTW89_CHANNEL_WIDTH_80) {
1815 if (chan->band_width == RTW89_CHANNEL_WIDTH_80) {
1836 if (rtwdev->hal.cv > CHIP_CAV)
1888 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1896 dpk->bp[path][kidx].ther_dpk = rtw89_read_rf(rtwdev, path, RR_TM, RR_TM_VAL);
1899 dpk->bp[path][kidx].ther_dpk);
1905 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1907 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
1923 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
1958 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1960 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80)
1962 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40)
1968 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
1969 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
1989 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2002 dpk->corr_idx[path][kidx] = corr_idx;
2003 dpk->corr_val[path][kidx] = corr_val;
2016 dpk->dc_i[path][kidx] = dc_i;
2017 dpk->dc_q[path][kidx] = dc_q;
2163 if (txagc - gain_offset < DPK_TXAGC_LOWER)
2165 else if (txagc - gain_offset > DPK_TXAGC_UPPER)
2168 txagc = txagc - gain_offset;
2269 if (chan->band_width < RTW89_CHANNEL_WIDTH_80)
2328 } while (!goout && agc_cnt < 6 && limit-- > 0);
2368 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2370 if (dpk->bp[path][kidx].bw < RTW89_CHANNEL_WIDTH_80 &&
2371 dpk->bp[path][kidx].band == RTW89_BAND_5G)
2382 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2384 u8 gs = dpk->dpk_gs[phy];
2393 dpk->bp[path][kidx].txagc_dpk = txagc;
2397 dpk->bp[path][kidx].pwsf = pwsf;
2404 dpk->bp[path][kidx].gs = gs;
2405 if (dpk->dpk_gs[phy] == 0x7f)
2422 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2426 cur_band = chan->band_type;
2427 cur_ch = chan->channel;
2430 if (cur_band != dpk->bp[path][idx].band ||
2431 cur_ch != dpk->bp[path][idx].ch)
2436 dpk->cur_idx[path] = idx;
2448 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2449 u8 txagc = 0x38, kidx = dpk->cur_idx[path];
2483 dpk->bp[path][kidx].path_ok = true;
2485 dpk->bp[path][kidx].path_ok = false;
2496 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2504 if (dpk->is_dpk_reload_en) {
2507 if (!reloaded[path] && dpk->bp[path][0].ch)
2508 dpk->cur_idx[path] = !dpk->cur_idx[path];
2514 dpk->cur_idx[path] = 0;
2523 if (rtwdev->is_tssi_mode[path])
2541 if (rtwdev->is_tssi_mode[path])
2549 struct rtw89_fem_info *fem = &rtwdev->fem;
2551 if (fem->epa_2g && chan->band_type == RTW89_BAND_2G) {
2555 } else if (fem->epa_5g && chan->band_type == RTW89_BAND_5G) {
2559 } else if (fem->epa_6g && chan->band_type == RTW89_BAND_6G) {
2584 RTW8852B_DPK_VER, rtwdev->hal.cv,
2595 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2605 kidx = dpk->cur_idx[path];
2609 path, kidx, dpk->bp[path][kidx].ch);
2611 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]);
2616 if (dpk->bp[path][kidx].ch && cur_ther)
2617 delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther;
2619 if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
2627 if (rtwdev->is_tssi_mode[path]) {
2667 pwsf[0] = dpk->bp[path][kidx].pwsf +
2668 txagc_bb_tp - txagc_bb + ini_diff;
2669 pwsf[1] = dpk->bp[path][kidx].pwsf +
2670 txagc_bb_tp - txagc_bb + ini_diff;
2672 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff;
2673 pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff;
2677 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2678 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff;
2699 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2709 dpk->dpk_gs[phy] = 0x7f;
2720 dpk->dpk_gs[phy] = 0x5b;
2728 enum rtw89_band band = chan->band_type;
2740 enum rtw89_band band = chan->band_type;
2794 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
2796 u8 ch = chan->channel;
2797 u8 subband = chan->subband_type;
2836 thermal = tssi_info->thermal[RF_PATH_A];
2864 -thm_down_a[i++] :
2865 -thm_down_a[DELTA_SWINGIDX_SIZE - 1];
2868 for (j = 63; j >= 32; j--)
2871 thm_up_a[DELTA_SWINGIDX_SIZE - 1];
2886 thermal = tssi_info->thermal[RF_PATH_B];
2914 -thm_down_b[i++] :
2915 -thm_down_b[DELTA_SWINGIDX_SIZE - 1];
2918 for (j = 63; j >= 32; j--)
2921 thm_up_b[DELTA_SWINGIDX_SIZE - 1];
2950 enum rtw89_band band = chan->band_type;
2966 enum rtw89_band band = chan->band_type;
2968 u8 ch = chan->channel;
3077 rtwdev->is_tssi_mode[RF_PATH_A] = true;
3097 rtwdev->is_tssi_mode[RF_PATH_B] = true;
3111 rtwdev->is_tssi_mode[RF_PATH_A] = false;
3112 rtwdev->is_tssi_mode[RF_PATH_B] = false;
3236 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3238 u8 ch = chan->channel;
3252 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
3253 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
3260 val = tssi_info->tssi_mcs[path][gidx];
3272 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3274 u8 ch = chan->channel;
3289 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
3290 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
3297 val = tssi_info->tssi_trim[path][tgidx];
3309 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3311 u8 ch = chan->channel;
3324 val = tssi_info->tssi_cck[i][gidx] + trim_de;
3328 i, gidx, tssi_info->tssi_cck[i][gidx], trim_de);
3388 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3390 u8 channel = chan->channel;
3407 if (tssi_info->alignment_done[path][band]) {
3409 tssi_info->alignment_value[path][band][0]);
3411 tssi_info->alignment_value[path][band][1]);
3413 tssi_info->alignment_value[path][band][2]);
3415 tssi_info->alignment_value[path][band][3]);
3482 channel_index = channel - 1;
3484 channel_index = (channel - 36) / 2 + 14;
3486 channel_index = ((channel - 100) / 2) + 15 + 14;
3488 channel_index = ((channel - 149) / 2) + 38 + 14;
3521 tx_counter_tmp -= tx_counter;
3537 tx_counter_tmp -= tx_counter;
3559 tx_counter_tmp -= tx_counter;
3576 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3580 u8 channel = chan->channel;
3596 if (tssi_info->check_backup_aligmk[path][ch_idx]) {
3598 tssi_info->alignment_backup_by_ch[path][ch_idx][0]);
3600 tssi_info->alignment_backup_by_ch[path][ch_idx][1]);
3602 tssi_info->alignment_backup_by_ch[path][ch_idx][2]);
3604 tssi_info->alignment_backup_by_ch[path][ch_idx][3]);
3614 if (chan->band_type == RTW89_BAND_2G)
3651 tssi_alim_offset_1 = tssi_cw_rpt[0] - ((power[0] - power[1]) * 2) -
3653 aliment_diff = tssi_alim_offset_1 - tssi_cw_default;
3695 tssi_info->alignment_done[path][band] = true;
3696 tssi_info->alignment_value[path][band][0] =
3698 tssi_info->alignment_value[path][band][1] =
3700 tssi_info->alignment_value[path][band][2] =
3702 tssi_info->alignment_value[path][band][3] =
3705 tssi_info->check_backup_aligmk[path][ch_idx] = true;
3706 tssi_info->alignment_backup_by_ch[path][ch_idx][0] =
3708 tssi_info->alignment_backup_by_ch[path][ch_idx][1] =
3710 tssi_info->alignment_backup_by_ch[path][ch_idx][2] =
3712 tssi_info->alignment_backup_by_ch[path][ch_idx][3] =
3716 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][0], 0x%x = 0x%08x\n",
3718 tssi_info->alignment_value[path][band][0]);
3720 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][1], 0x%x = 0x%08x\n",
3722 tssi_info->alignment_value[path][band][1]);
3724 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][2], 0x%x = 0x%08x\n",
3726 tssi_info->alignment_value[path][band][2]);
3728 "[TSSI PA K] tssi_info->alignment_value[path=%d][band=%d][3], 0x%x = 0x%08x\n",
3730 tssi_info->alignment_value[path][band][3]);
3738 tssi_info->tssi_alimk_time += finish_time - start_time;
3742 tssi_info->tssi_alimk_time);
3807 rtwdev->dpk.is_dpk_enable = true;
3808 rtwdev->dpk.is_dpk_reload_en = false;
3860 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3861 u8 channel = chan->channel;
3886 if (tssi_info->alignment_done[i][band])
3900 u8 channel = chan->channel;
3906 if (!rtwdev->is_tssi_mode[RF_PATH_A] && !rtwdev->is_tssi_mode[RF_PATH_B])
3957 "[RFK]Invalid RF_0x18 for Path-%d\n", path);
4033 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]re-set RF 0x18\n");
4105 "[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n",
4167 rtw8852b_ctrl_bw_ch(rtwdev, phy_idx, chan->channel, chan->band_type,
4168 chan->band_width);