Lines Matching +full:ignore +full:- +full:power +full:- +full:on +full:- +full:sel
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
41 u32 val, enum rtw89_mac_mem_sel sel)
43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
44 u32 addr = mac->mem_base_addrs[sel] + offset;
46 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
47 rtw89_write32(rtwdev, mac->indir_access_addr, val);
51 enum rtw89_mac_mem_sel sel)
53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
54 u32 addr = mac->mem_base_addrs[sel] + offset;
56 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
57 return rtw89_read32(rtwdev, mac->indir_access_addr);
61 enum rtw89_mac_hwmod_sel sel)
65 if (sel == RTW89_DMAC_SEL) {
68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) {
71 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) {
75 return -EINVAL;
79 return -EFAULT;
122 switch (ctrl->type) {
126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) |
127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) |
133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) |
134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) |
138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type);
139 return -EINVAL;
152 ctrl->out_data = rtw89_read32(rtwdev, data_reg);
162 ctrl.type = quota->dle_type;
164 ctrl.addr = quota->qtaid;
171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data);
172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data);
182 ctrl.type = qempty->dle_type;
184 ctrl.addr = qempty->grpsel;
191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data);
305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
314 mac->dump_qta_lost(rtwdev);
323 const struct rtw89_chip_info *chip = rtwdev->chip;
343 if (chip->chip_id == RTL8852C) {
360 if (chip->chip_id == RTL8852C)
369 if (chip->chip_id == RTL8852C) {
398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
401 } else if (chip->chip_id == RTL8922A) {
452 if (chip->chip_id == RTL8922A) {
477 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) {
515 if (chip->chip_id == RTL8922A) {
529 if (chip->chip_id == RTL8852C) {
555 if (chip->chip_id == RTL8922A) {
585 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) {
610 if (chip->chip_id == RTL8922A) {
619 if (chip->chip_id == RTL8922A) {
624 } else if (chip->chip_id == RTL8852C) {
659 const struct rtw89_chip_info *chip = rtwdev->chip;
699 if (chip->chip_id == RTL8852C) {
711 if (chip->chip_id == RTL8852C) {
730 if (chip->chip_id == RTL8852C) {
757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
771 rtwdev->hci.ops->dump_err_status(rtwdev);
776 rtw89_info(rtwdev, "<---\n");
781 struct rtw89_ser *ser = &rtwdev->ser;
785 if (rtwdev->chip->chip_id == RTL8852C) {
797 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags);
801 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags))
804 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags))
814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
840 mac->dump_err_status(rtwdev, err);
848 struct rtw89_ser *ser = &rtwdev->ser;
853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err);
854 return -EINVAL;
861 return -EFAULT;
866 if (ser->prehandle_l1 &&
878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
882 switch (rtwdev->hci.type) {
884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode];
885 param->en = 0;
888 return -EINVAL;
892 param->pub_cfg = *param_ini.pub_cfg;
895 param->prec_cfg = *param_ini.prec_cfg;
898 param->ch_cfg = param_ini.ch_cfg;
900 memset(¶m->ch_info, 0, sizeof(param->ch_info));
901 memset(¶m->pub_info, 0, sizeof(param->pub_info));
902 param->mode = param_ini.mode;
909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
910 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg;
911 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
912 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
915 return -EINVAL;
917 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) ||
918 ch_cfg[ch].max > pub_cfg->pub_max)
919 return -EINVAL;
921 return -EINVAL;
928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
929 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg;
930 struct rtw89_hfc_pub_info *info = ¶m->pub_info;
932 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) {
933 if (rtwdev->chip->chip_id == RTL8852A)
936 return -EFAULT;
944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
945 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
947 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max)
948 return -EFAULT;
955 const struct rtw89_chip_info *chip = rtwdev->chip;
956 const struct rtw89_page_regs *regs = chip->page_regs;
957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
958 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
971 return -EINVAL;
976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);
983 const struct rtw89_chip_info *chip = rtwdev->chip;
984 const struct rtw89_page_regs *regs = chip->page_regs;
985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
986 struct rtw89_hfc_ch_info *info = param->ch_info;
987 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
996 return -EINVAL;
998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);
1003 info[ch].used = cfg[ch].min - info[ch].aval;
1010 const struct rtw89_chip_info *chip = rtwdev->chip;
1011 const struct rtw89_page_regs *regs = chip->page_regs;
1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg;
1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) |
1025 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK);
1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);
1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK);
1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);
1036 const struct rtw89_chip_info *chip = rtwdev->chip;
1037 const struct rtw89_page_regs *regs = chip->page_regs;
1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1039 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
1040 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
1041 struct rtw89_hfc_pub_info *info = ¶m->pub_info;
1044 val = rtw89_read32(rtwdev, regs->pub_page_info1);
1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK);
1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK);
1047 val = rtw89_read32(rtwdev, regs->pub_page_info3);
1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK);
1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK);
1050 info->pub_aval =
1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2),
1053 info->wp_aval =
1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1),
1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0;
1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0;
1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK);
1061 prec_cfg->ch011_full_cond =
1063 prec_cfg->h2c_full_cond =
1065 prec_cfg->wp_ch07_full_cond =
1067 prec_cfg->wp_ch811_full_cond =
1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl);
1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK);
1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK);
1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);
1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK);
1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);
1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK);
1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK);
1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);
1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK);
1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);
1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK);
1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK);
1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1099 mac->hfc_get_mix_info(rtwdev);
1102 if (param->en && ret)
1110 const struct rtw89_chip_info *chip = rtwdev->chip;
1111 const struct rtw89_page_regs *regs = chip->page_regs;
1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1113 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl,
1121 prec_cfg->h2c_full_cond);
1126 const struct rtw89_chip_info *chip = rtwdev->chip;
1127 const struct rtw89_page_regs *regs = chip->page_regs;
1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1129 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
1130 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) |
1134 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK);
1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);
1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec,
1142 u32_encode_bits(prec_cfg->wp_ch811_prec,
1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);
1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),
1147 param->mode, B_AX_HCI_FC_MODE_MASK);
1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1161 const struct rtw89_chip_info *chip = rtwdev->chip;
1162 const struct rtw89_page_regs *regs = chip->page_regs;
1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1167 param->en = en;
1168 param->h2c_en = h2c_en;
1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1178 const struct rtw89_chip_info *chip = rtwdev->chip;
1179 u32 dma_ch_mask = chip->dma_ch_mask;
1192 mac->hfc_func_en(rtwdev, false, false);
1195 mac->hfc_h2c_cfg(rtwdev);
1196 mac->hfc_func_en(rtwdev, en, h2c_en);
1212 mac->hfc_mix_cfg(rtwdev);
1214 mac->hfc_func_en(rtwdev, en, h2c_en);
1235 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ?
1236 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr;
1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk),
1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr);
1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);
1248 return -EBUSY;
1258 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) {
1259 if (!(cur_cfg->intf_msk & intf_msk) ||
1260 !(cur_cfg->cv_msk & cv_msk))
1263 switch (cur_cfg->cmd) {
1265 addr = cur_cfg->addr;
1267 if (cur_cfg->base == PWR_BASE_SDIO)
1271 val &= ~(cur_cfg->msk);
1272 val |= (cur_cfg->val & cur_cfg->msk);
1278 return -EBUSY;
1281 if (cur_cfg->val == PWR_DELAY_US)
1282 udelay(cur_cfg->addr);
1284 fsleep(cur_cfg->addr * 1000);
1287 return -EINVAL;
1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv),
1303 return -EBUSY;
1314 switch (rtwdev->ps_mode) {
1337 spin_lock_bh(&rtwdev->rpwm_lock);
1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) &
1349 rtwdev->mac.rpwm_seq_num);
1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request);
1356 spin_unlock_bh(&rtwdev->rpwm_lock);
1380 return -EPERM;
1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num;
1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr,
1390 return -EPERM;
1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) &
1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM);
1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num)
1397 return -EPERM;
1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE);
1401 return -EPERM;
1426 if (i == RPWM_TRY_CNT - 1)
1444 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)
1447 const struct rtw89_chip_info *chip = rtwdev->chip;
1453 if (on) {
1454 cfg_seq = chip->pwr_on_seq;
1455 cfg_func = chip->ops->pwr_on_func;
1457 cfg_seq = chip->pwr_off_seq;
1458 cfg_func = chip->ops->pwr_off_func;
1461 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
1465 if (on && val == PWR_ACT) {
1466 rtw89_err(rtwdev, "MAC has already powered on\n");
1467 return -EBUSY;
1474 if (on) {
1475 set_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1476 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
1477 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
1480 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1481 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
1482 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
1483 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
1484 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
1546 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1580 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1692 struct rtw89_mac_info *mac = &rtwdev->mac;
1695 cfg = &rtwdev->chip->dle_mem[mode];
1699 if (cfg->mode != mode) {
1704 mac->dle_info.rsvd_qt = cfg->rsvd_qt;
1705 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size;
1706 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num;
1707 mac->dle_info.qta_mode = mode;
1708 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma;
1709 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma;
1718 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info;
1719 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt;
1723 cfg->pktid = dle_info->ple_free_pg;
1724 cfg->pg_num = rsvd_qt->mpdu_info_tbl;
1727 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl;
1728 cfg->pg_num = rsvd_qt->b0_csi;
1731 cfg->pktid = dle_info->ple_free_pg +
1732 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi;
1733 cfg->pg_num = rsvd_qt->b1_csi;
1736 cfg->pktid = dle_info->ple_free_pg +
1737 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi;
1738 cfg->pg_num = rsvd_qt->b0_lmr;
1741 cfg->pktid = dle_info->ple_free_pg +
1742 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi +
1743 rsvd_qt->b0_lmr;
1744 cfg->pg_num = rsvd_qt->b1_lmr;
1747 cfg->pktid = dle_info->ple_free_pg +
1748 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi +
1749 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr;
1750 cfg->pg_num = rsvd_qt->b0_ftm;
1753 cfg->pktid = dle_info->ple_free_pg +
1754 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi +
1755 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm;
1756 cfg->pg_num = rsvd_qt->b1_ftm;
1759 return -EINVAL;
1762 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size;
1773 grpnum = rtwdev->chip->wde_qempty_acq_grpnum;
1792 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel;
1802 if (rtwdev->dbcc_en) {
1823 const struct rtw89_dle_size *wde = cfg->wde_size;
1824 const struct rtw89_dle_size *ple = cfg->ple_size;
1827 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) +
1828 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num);
1830 if (cfg->rsvd0_size && cfg->rsvd1_size) {
1831 used += cfg->rsvd0_size->size;
1832 used += cfg->rsvd1_size->size;
1841 u32 size = rtwdev->chip->fifo_size;
1844 size -= rtwdev->chip->dle_scc_rsvd_size;
1864 if (rtwdev->chip->chip_id == RTL8851B)
1879 size_cfg = cfg->wde_size;
1881 switch (size_cfg->pge_size) {
1893 return -EINVAL;
1897 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1902 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num)
1903 * size_cfg->pge_size / DLE_BOUND_UNIT;
1904 size_cfg = cfg->ple_size;
1906 switch (size_cfg->pge_size) {
1910 return -EINVAL;
1922 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1956 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
1964 ext_wde_min_qt_wcpu : min_cfg->wcpu;
1968 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1);
1990 if (rtwdev->chip->chip_id == RTL8852C)
2000 if (rtwdev->chip->chip_id == RTL8852C)
2003 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) {
2005 return -EINVAL;
2014 return -EINVAL;
2017 min_cfg = cfg->ple_min_qt;
2018 max_cfg = cfg->ple_max_qt;
2030 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
2043 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2045 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu);
2046 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt);
2052 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2064 ret = -EINVAL;
2073 ret = -EINVAL;
2076 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu;
2081 ret = -EINVAL;
2085 mac->dle_func_en(rtwdev, false);
2086 mac->dle_clk_en(rtwdev, true);
2088 ret = mac->dle_mix_cfg(rtwdev, cfg);
2095 mac->dle_func_en(rtwdev, true);
2097 ret = mac->chk_dle_rdy(rtwdev, true);
2103 ret = mac->chk_dle_rdy(rtwdev, false);
2111 mac->dle_func_en(rtwdev, false);
2143 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
2149 const struct rtw89_chip_info *chip = rtwdev->chip;
2151 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) ||
2186 const struct rtw89_chip_info *chip = rtwdev->chip;
2188 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
2243 const struct rtw89_chip_info *chip = rtwdev->chip;
2257 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
2258 chip->chip_id == RTL8851B)
2269 if (chip->chip_id == RTL8852C)
2280 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
2286 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode);
2357 if (rtwdev->chip->chip_id == RTL8852C)
2373 if (rtwdev->chip->chip_id == RTL8852C) {
2407 return -EINVAL;
2422 return -EINVAL;
2444 mac_ftlr = rtwdev->hal.rx_fltr;
2468 switch (rtwdev->chip->chip_id) {
2574 const struct rtw89_chip_info *chip = rtwdev->chip;
2575 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs;
2588 switch (rtwdev->chip->chip_id) {
2608 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx);
2609 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
2610 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx);
2611 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);
2638 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2668 rx_qta = rtwdev->mac.dle_info.c0_rx_qta;
2670 rx_qta = rtwdev->mac.dle_info.c1_rx_qta;
2672 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size;
2677 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) {
2693 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2726 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma);
2738 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
2877 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2881 mac->cnv_efuse_state(rtwdev, false);
2890 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP)
2891 ret = -EINVAL;
2894 mac->cnv_efuse_state(rtwdev, true);
2901 struct rtw89_efuse *efuse = &rtwdev->efuse;
2902 struct rtw89_hal *hal = &rtwdev->hal;
2903 const struct rtw89_chip_info *chip = rtwdev->chip;
2918 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS);
2919 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS);
2920 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM);
2921 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM);
2923 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss;
2924 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss;
2927 hal->antenna_tx = RF_B;
2929 hal->antenna_rx = RF_B;
2932 hal->antenna_tx = RF_B;
2933 hal->tx_path_diversity = true;
2936 if (chip->rf_path_num == 1) {
2937 hal->antenna_tx = RF_A;
2938 hal->antenna_rx = RF_A;
2939 if ((efuse->rfe_type % 3) == 2)
2940 hal->ant_diversity = true;
2945 hal->tx_nss, tx_nss, chip->tx_nss,
2946 hal->rx_nss, rx_nss, chip->rx_nss);
2949 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx);
2950 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity);
2951 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity);
2965 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN;
2967 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN);
2968 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK);
2969 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND);
2976 return -EINVAL;
2992 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
3022 u32 *tx_en, enum rtw89_sch_tx_sel sel)
3029 switch (sel) {
3063 u32 *tx_en, enum rtw89_sch_tx_sel sel)
3070 switch (sel) {
3147 return -ENOENT;
3158 cmd_type = ctrl_para->cmd_type;
3162 val = u32_replace_bits(val, ctrl_para->start_pktid,
3164 val = u32_replace_bits(val, ctrl_para->end_pktid,
3170 val = u32_replace_bits(val, ctrl_para->src_pid,
3172 val = u32_replace_bits(val, ctrl_para->src_qid,
3174 val = u32_replace_bits(val, ctrl_para->dst_pid,
3176 val = u32_replace_bits(val, ctrl_para->dst_qid,
3184 val = u32_replace_bits(val, ctrl_para->macid,
3186 val = u32_replace_bits(val, ctrl_para->pkt_num,
3200 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val);
3208 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3214 return -EINVAL;
3219 return -EINVAL;
3224 return mac->dle_quota_change(rtwdev, band1_en);
3229 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3234 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id);
3246 ret = mac->set_cpuio(rtwdev, &ctrl_para, true);
3249 return -EFAULT;
3252 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id);
3264 ret = mac->set_cpuio(rtwdev, &ctrl_para, false);
3267 return -EFAULT;
3322 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true);
3359 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3362 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
3367 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3369 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
3374 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3375 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3390 imr->mpdu_tx_imr_set);
3397 imr->mpdu_rx_imr_set);
3402 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3409 imr->sta_sch_imr_set);
3414 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3416 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
3417 imr->txpktctl_imr_b0_clr);
3418 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
3419 imr->txpktctl_imr_b0_set);
3420 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
3421 imr->txpktctl_imr_b1_clr);
3422 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
3423 imr->txpktctl_imr_b1_set);
3428 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3430 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
3431 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
3436 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3438 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
3439 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
3450 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3453 imr->host_disp_imr_clr);
3455 imr->host_disp_imr_set);
3457 imr->cpu_disp_imr_clr);
3459 imr->cpu_disp_imr_set);
3461 imr->other_disp_imr_clr);
3463 imr->other_disp_imr_set);
3474 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3476 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
3478 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3480 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3481 imr->bbrpt_err_imr_set);
3482 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
3499 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3503 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
3504 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
3509 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3510 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3513 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx);
3514 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
3515 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
3518 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx);
3519 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
3520 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
3526 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3529 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx);
3530 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
3531 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
3536 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3539 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx);
3540 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
3541 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
3546 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3549 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx);
3550 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
3551 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);
3555 enum rtw89_mac_hwmod_sel sel)
3559 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel);
3562 sel, mac_idx);
3566 if (sel == RTW89_DMAC_SEL) {
3578 } else if (sel == RTW89_CMAC_SEL) {
3586 return -EINVAL;
3598 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta)
3621 return -EINVAL;
3629 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
3649 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3650 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;
3705 const struct rtw89_chip_info *chip = rtwdev->chip;
3708 if (chip->bacam_ver != RTW89_BACAM_V1)
3743 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
3763 return -EFAULT;
3784 if (rtwdev->chip->chip_id == RTL8852B)
3805 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3819 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3848 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3851 mac->hci_func_en(rtwdev);
3852 mac->dmac_func_pre_en(rtwdev);
3854 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode);
3911 if (rtwdev->dbcc_en)
3919 if (rtwdev->hci.ops->mac_pre_init) {
3920 ret = rtwdev->hci.ops->mac_pre_init(rtwdev);
3934 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3935 const struct rtw89_chip_info *chip = rtwdev->chip;
3936 bool include_bb = !!chip->bbmcu_nr;
3947 ret = mac->sys_init(rtwdev);
3951 ret = mac->trx_init(rtwdev);
3959 if (rtwdev->hci.ops->mac_post_init) {
3960 ret = rtwdev->hci.ops->mac_post_init(rtwdev);
3979 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
3991 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
4013 * be power-off, so ignore this operation.
4015 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) &&
4016 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4060 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4061 const struct rtw89_port_reg *p = mac->port_base;
4062 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif->port);
4067 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif->mac_idx);
4068 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif->mac_idx);
4082 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4083 const struct rtw89_port_reg *p = mac->port_base;
4085 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif->port));
4086 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 1);
4087 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 0);
4088 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 0);
4089 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 2);
4090 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK, 1);
4091 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 1);
4092 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
4095 if (rtwvif->port == RTW89_PORT_0)
4098 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif->port));
4099 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TBTT_PROHIB_EN);
4115 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4116 const struct rtw89_port_reg *p = mac->port_base;
4118 const struct rtw89_chip_info *chip = rtwdev->chip;
4122 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN))
4125 if (chip->chip_id == RTL8852A && rtwvif->port != RTW89_PORT_0) {
4127 backup_val = rtw89_read32_port(rtwdev, rtwvif, p->tbtt_prohib);
4130 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE)
4133 if (chip->chip_id == RTL8852A) {
4134 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK);
4135 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1);
4136 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK);
4137 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK);
4140 msleep(vif->bss_conf.beacon_int + 1);
4141 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN |
4143 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST);
4144 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0);
4147 rtw89_write32_port(rtwdev, rtwvif, p->tbtt_prohib, backup_val);
4153 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4154 const struct rtw89_port_reg *p = mac->port_base;
4157 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
4159 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
4165 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4166 const struct rtw89_port_reg *p = mac->port_base;
4169 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
4171 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
4177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4178 const struct rtw89_port_reg *p = mac->port_base;
4180 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK,
4181 rtwvif->net_type);
4187 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4188 const struct rtw89_port_reg *p = mac->port_base;
4189 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK;
4193 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits);
4195 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits);
4201 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4202 const struct rtw89_port_reg *p = mac->port_base;
4203 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA ||
4204 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
4208 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit);
4210 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit);
4216 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4217 const struct rtw89_port_reg *p = mac->port_base;
4220 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
4222 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
4228 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA ||
4229 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
4237 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4238 const struct rtw89_port_reg *p = mac->port_base;
4241 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
4243 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
4249 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ||
4250 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
4260 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE)
4267 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4268 const struct rtw89_port_reg *p = mac->port_base;
4270 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL;
4272 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK,
4279 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0;
4280 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4281 const struct rtw89_port_reg *p = mac->port_base;
4282 u8 port = rtwvif->port;
4285 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx);
4292 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4293 const struct rtw89_port_reg *p = mac->port_base;
4297 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx);
4300 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK,
4301 vif->bss_conf.dtim_period);
4307 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4308 const struct rtw89_port_reg *p = mac->port_base;
4310 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
4317 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4318 const struct rtw89_port_reg *p = mac->port_base;
4320 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
4327 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4328 const struct rtw89_port_reg *p = mac->port_base;
4330 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area,
4337 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4338 const struct rtw89_port_reg *p = mac->port_base;
4340 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early,
4347 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4348 const struct rtw89_port_reg *p = mac->port_base;
4355 u8 port = rtwvif->port;
4360 bss_color = vif->bss_conf.he_bss_color.color;
4361 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color;
4362 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx);
4369 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4370 const struct rtw89_port_reg *p = mac->port_base;
4371 u8 port = rtwvif->port;
4374 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE)
4378 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx);
4386 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4387 const struct rtw89_port_reg *p = mac->port_base;
4388 u8 port = rtwvif->port;
4392 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx);
4403 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4404 const struct rtw89_port_reg *p = mac->port_base;
4407 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg,
4410 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg,
4417 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4418 const struct rtw89_port_reg *p = mac->port_base;
4420 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK,
4427 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4428 const struct rtw89_port_reg *p = mac->port_base;
4431 if (rtwdev->chip->chip_id != RTL8852C)
4434 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT &&
4435 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION)
4441 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift,
4450 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4451 const struct rtw89_port_reg *p = mac->port_base;
4455 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4,
4456 rtwvif->mac_idx);
4458 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port);
4468 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src)
4472 offset = offset - offset / 4 + get_random_u32() % (offset / 2);
4486 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA)
4488 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE)
4509 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id);
4510 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id);
4512 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false);
4562 u8 port = rtwvif->port;
4565 return -EINVAL;
4597 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4598 const struct rtw89_port_reg *p = mac->port_base;
4602 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL);
4606 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l);
4607 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h);
4622 ies = rcu_dereference(bss->ies);
4623 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data,
4624 ies->len);
4626 if (!elem || elem->datalen < 10 ||
4627 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT))
4635 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4636 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4637 struct ieee80211_hw *hw = rtwdev->hw;
4641 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION)
4644 if (!(vif->bss_conf.chanreq.oper.chan->flags & IEEE80211_CHAN_RADAR))
4647 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chanreq.oper,
4651 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr,
4652 rtwvif->mac_idx);
4654 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask);
4656 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask);
4668 rtwvif->mac_id = rtw89_acquire_mac_id(rtwdev);
4669 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM)
4670 return -ENOSPC;
4679 rtw89_release_mac_id(rtwdev, rtwvif->mac_id);
4689 rtw89_release_mac_id(rtwdev, rtwvif->mac_id);
4701 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
4703 return band == op->band_type && channel == op->primary_channel;
4711 (const struct rtw89_c2h_scanofld *)skb->data;
4712 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
4716 u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf;
4724 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL);
4725 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS);
4726 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH);
4727 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN);
4728 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND);
4729 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD);
4730 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX);
4733 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))
4740 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
4741 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF);
4742 expect_period = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD);
4743 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF);
4744 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF);
4756 ieee80211_stop_queues(rtwdev->hw);
4760 if (rtwdev->scan_info.abort)
4763 if (rtwvif && rtwvif->scan_req &&
4764 last_chan < rtwvif->scan_req->n_channels) {
4777 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx,
4778 &rtwdev->scan_info.op_chan);
4780 ieee80211_wake_queues(rtwdev->hw);
4784 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx,
4800 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data;
4804 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE);
4805 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI;
4806 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT);
4807 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID);
4809 if (mac_id != rtwvif->mac_id)
4818 if (!rtwdev->scanning && !rtwvif->offchan)
4858 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data),
4859 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data),
4860 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data),
4861 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data));
4868 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
4870 (const struct rtw89_c2h_done_ack *)skb_c2h->data;
4871 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT);
4872 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS);
4873 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC);
4874 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN);
4875 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ);
4913 rtw89_fw_log_dump(rtwdev, c2h->data, len);
4925 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
4927 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data;
4928 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN);
4929 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID);
4930 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP);
4953 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data);
4954 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data);
4980 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data);
4981 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data);
4982 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data);
5015 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5021 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data);
5027 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data);
5028 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data);
5029 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data);
5030 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data);
5031 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data);
5032 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data);
5037 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low,
5038 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low);
5041 rpt->macid_x, (uintmax_t)rpt->tsf_x_high << 32 | rpt->tsf_x_low,
5042 rpt->macid_y, (uintmax_t)rpt->tsf_y_high << 32 | rpt->tsf_y_low);
5046 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5052 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data);
5053 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data);
5054 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data);
5055 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data);
5056 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data);
5121 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5127 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
5133 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data;
5135 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM,
5136 le32_get_bits(c2h_rpt->w2,
5139 for (i = 0; i < rpt->num; i++) {
5140 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high);
5141 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low);
5143 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low;
5148 i, rpt->tsfs[i]);
5151 i, (uintmax_t)rpt->tsfs[i]);
5161 struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
5162 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt;
5163 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
5165 (const struct rtw89_c2h_wow_aoac_report *)skb->data;
5169 aoac_rpt->rpt_ver = c2h->rpt_ver;
5170 aoac_rpt->sec_type = c2h->sec_type;
5171 aoac_rpt->key_idx = c2h->key_idx;
5172 aoac_rpt->pattern_idx = c2h->pattern_idx;
5173 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok,
5175 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv));
5176 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count,
5177 sizeof(aoac_rpt->eapol_key_replay_count));
5178 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk));
5179 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv));
5180 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv));
5181 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id);
5182 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn);
5183 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk));
5192 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
5203 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data;
5204 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX);
5205 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS);
5206 tsf_high = le32_to_cpu(c2h_rpt->tsf_high);
5207 tsf_low = le32_to_cpu(c2h_rpt->tsf_low);
5255 "MRC C2H STS RPT: tx null-0 fail\n");
5331 (const struct rtw89_c2h_scanofld *)skb->data;
5332 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
5337 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS);
5338 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN);
5342 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
5430 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode;
5490 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
5491 struct ieee80211_hw *hw = rtwdev->hw;
5492 u32 rts_threshold = hw->wiphy->rts_threshold;
5496 if (rts_threshold == (u32)-1) {
5507 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx);
5517 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5522 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning))
5528 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
5559 switch (coex->pta_mode) {
5593 return -EINVAL;
5596 switch (coex->direction) {
5613 return -EINVAL;
5629 switch (coex->pta_mode) {
5641 return -EINVAL;
5653 if (gnt_cfg->band[0].gnt_bt)
5656 if (gnt_cfg->band[0].gnt_bt_sw_en)
5659 if (gnt_cfg->band[0].gnt_wl)
5662 if (gnt_cfg->band[0].gnt_wl_sw_en)
5665 if (gnt_cfg->band[1].gnt_bt)
5668 if (gnt_cfg->band[1].gnt_bt_sw_en)
5671 if (gnt_cfg->band[1].gnt_wl)
5674 if (gnt_cfg->band[1].gnt_wl_sw_en)
5692 if (gnt_cfg->band[0].gnt_bt)
5698 if (gnt_cfg->band[0].gnt_bt_sw_en)
5702 if (gnt_cfg->band[0].gnt_wl)
5706 if (gnt_cfg->band[0].gnt_wl_sw_en)
5710 if (gnt_cfg->band[1].gnt_bt)
5716 if (gnt_cfg->band[1].gnt_bt_sw_en)
5720 if (gnt_cfg->band[1].gnt_wl)
5724 if (gnt_cfg->band[1].gnt_wl_sw_en)
5741 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);
5745 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band);
5746 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) |
5747 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) |
5748 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) |
5749 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) |
5750 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) |
5751 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) |
5752 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) |
5753 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) |
5767 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5797 struct rtw89_btc *btc = &rtwdev->btc;
5798 struct rtw89_btc_dm *dm = &btc->dm;
5799 struct rtw89_mac_ax_gnt *g = dm->gnt.band;
5812 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt);
5818 const struct rtw89_chip_info *chip = rtwdev->chip;
5821 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A)
5823 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
5847 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
5853 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
5857 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
5865 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
5867 u32 mask = mac->bfee_ctrl.mask;
5870 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx);
5872 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
5875 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
5926 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5927 u8 mac_idx = rtwvif->mac_idx;
5929 u8 port_sel = rtwvif->port;
5931 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info;
5948 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
5949 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
5950 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC);
5951 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK);
5953 sta->deflink.vht_cap.cap);
5984 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5987 u8 mac_idx = rtwvif->mac_idx;
5994 if (sta->deflink.he_cap.has_he) {
5999 if (sta->deflink.vht_cap.vht_supported) {
6004 if (sta->deflink.ht_cap.ht_supported) {
6023 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
6028 rtw89_mac_init_bfee_ax(rtwdev, rtwvif->mac_idx);
6037 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
6039 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false);
6045 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
6046 u8 mac_idx = rtwvif->mac_idx;
6051 p = (__le32 *)conf->mu_group.membership;
6059 p = (__le32 *)conf->mu_group.position;
6081 struct ieee80211_sta *down_sta = iter_data->down_sta;
6082 int *count = &iter_data->count;
6099 ieee80211_iterate_stations_atomic(rtwdev->hw,
6105 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
6107 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
6112 struct rtw89_traffic_stats *stats = &rtwdev->stats;
6114 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv;
6115 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
6119 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
6121 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW)
6126 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx,
6134 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en);
6142 u8 mac_idx = rtwsta->rtwvif->mac_idx;
6147 if (rtwsta->cctl_tx_time) {
6148 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9;
6171 rtwsta->cctl_tx_time = true;
6175 rtwsta->cctl_tx_time = false;
6184 u8 mac_idx = rtwsta->rtwvif->mac_idx;
6188 if (rtwsta->cctl_tx_time) {
6189 *tx_time = (rtwsta->ampdu_max_time + 1) << 9;
6210 rtwsta->data_tx_cnt_lmt = tx_retry;
6213 rtwsta->cctl_tx_retry_limit = true;
6217 rtwsta->cctl_tx_retry_limit = false;
6226 u8 mac_idx = rtwsta->rtwvif->mac_idx;
6230 if (rtwsta->cctl_tx_retry_limit) {
6231 *tx_retry = rtwsta->data_tx_cnt_lmt;
6249 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6250 u8 mac_idx = rtwvif->mac_idx;
6251 u16 set = mac->muedca_ctrl.mask;
6259 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx);
6326 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
6331 params.macid = rtwsta->mac_id;
6332 params.port = rtwvif->port;
6334 params.tf_trs = rtwvif->trigger;
6337 params.sel = sels[i];
6344 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
6345 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
6346 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
6357 ieee80211_iterate_stations_atomic(rtwdev->hw,
6365 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6371 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE;
6374 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50,
6376 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw))
6399 ret = -EINVAL;
6406 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6407 const struct rtw89_chip_info *chip = rtwdev->chip;
6419 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE);
6426 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))