Lines Matching defs:rtwdev
40 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
46 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
47 rtw89_write32(rtwdev, mac->indir_access_addr, val);
50 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset,
53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
56 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
57 return rtw89_read32(rtwdev, mac->indir_access_addr);
60 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx,
66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN);
69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN);
72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND);
84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val)
90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val);
95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset);
100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val)
106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset);
111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA);
116 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl)
138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type);
142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data);
145 1, 1000, false, rtwdev, ctrl_reg);
147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n",
152 ctrl->out_data = rtw89_read32(rtwdev, data_reg);
156 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev,
165 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl);
167 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret);
176 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev,
185 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl);
187 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret);
195 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev)
197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ",
198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n",
200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ",
202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n",
204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ",
206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n",
208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
211 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev)
222 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty);
235 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl);
237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
239 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i,
246 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a);
248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n",
253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG);
254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n",
256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n",
258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT);
259 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n",
261 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n",
262 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG));
263 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n",
264 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0));
265 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n",
266 rtw89_read32(rtwdev, R_AX_CCA_CONTROL));
268 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) {
271 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a);
273 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
275 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n",
278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG);
279 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n",
281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n",
283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1);
284 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n",
286 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n",
287 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1));
288 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n",
289 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1));
290 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n",
291 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1));
294 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n",
295 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0));
296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n",
297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1));
299 dump_err_status_dispatcher_ax(rtwdev);
302 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
308 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO);
313 rtw89_info(rtwdev, "quota lost!\n");
314 mac->dump_qta_lost(rtwdev);
321 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev)
323 const struct rtw89_chip_info *chip = rtwdev->chip;
327 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
329 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n");
333 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
334 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);
335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n",
336 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));
339 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",
340 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));
341 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",
342 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));
344 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",
345 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));
346 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",
347 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));
348 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",
349 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));
350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n",
351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));
356 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n",
357 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n",
359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
361 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
362 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));
364 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
365 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));
370 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n",
371 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));
372 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n",
373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));
374 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
375 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
376 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
377 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
378 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
379 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
380 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
381 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
382 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n",
383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));
384 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
385 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
386 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
387 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
399 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));
402 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n",
403 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG));
404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n",
405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR));
406 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n",
407 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL));
408 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n",
409 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC));
410 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n",
411 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS));
412 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n",
413 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA));
414 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n",
415 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2));
417 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
418 rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
419 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
420 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
421 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
422 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
423 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
424 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
425 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
426 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
427 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n",
428 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
429 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
430 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
431 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
432 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
433 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",
434 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
435 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",
436 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
441 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",
442 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
445 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",
446 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
453 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n",
454 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG));
455 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n",
456 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG));
458 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",
459 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
466 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
467 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
468 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
469 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
470 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
471 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
472 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
473 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
478 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
479 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
487 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
488 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
495 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
496 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
497 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
498 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
499 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
500 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
501 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
502 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
503 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
504 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
509 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
510 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
516 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n",
517 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3));
518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n",
519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS));
520 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n",
521 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3));
522 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n",
523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS));
525 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
526 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
527 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
528 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
530 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n",
531 rtw89_read32(rtwdev, R_AX_RX_CTRL0));
532 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n",
533 rtw89_read32(rtwdev, R_AX_RX_CTRL1));
534 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n",
535 rtw89_read32(rtwdev, R_AX_RX_CTRL2));
537 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
538 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
548 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n",
549 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n",
551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
556 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n",
557 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR));
558 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n",
559 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1));
560 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n",
561 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR));
562 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n",
563 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2));
564 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n",
565 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR));
566 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n",
567 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0));
569 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
570 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
573 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
574 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
577 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",
578 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
586 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
587 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));
588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));
590 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
591 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
594 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
595 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
599 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
600 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
601 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
602 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
605 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
606 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
611 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n",
612 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR));
613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n",
614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR));
620 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n",
621 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK));
622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n",
623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT));
625 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
626 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));
627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT));
633 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n",
634 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK,
636 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n",
637 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT,
642 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n",
643 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR));
644 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n",
645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR));
649 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n",
650 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR));
651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n",
652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR));
656 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev,
659 const struct rtw89_chip_info *chip = rtwdev->chip;
664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
667 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n");
669 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n");
676 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);
677 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,
678 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));
679 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,
680 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));
681 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band,
682 rtw89_read32(rtwdev, R_AX_CK_EN + offset));
685 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
686 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));
687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));
692 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band,
693 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));
694 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band,
695 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));
700 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,
701 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));
702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band,
703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));
705 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band,
706 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));
712 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
713 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));
714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
717 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
718 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
723 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band,
724 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));
725 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band,
726 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));
731 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
732 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset));
733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));
736 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band,
737 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset));
739 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
740 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));
743 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,
744 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));
747 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev,
757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
758 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
759 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
762 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n",
763 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4));
764 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n",
765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5));
767 rtw89_mac_dump_dmac_err_status(rtwdev);
768 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0);
769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1);
771 rtwdev->hci.ops->dump_err_status(rtwdev);
774 rtw89_mac_dump_l0_to_l1(rtwdev, err);
776 rtw89_info(rtwdev, "<---\n");
779 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err)
781 struct rtw89_ser *ser = &rtwdev->ser;
785 if (rtwdev->chip->chip_id == RTL8852C) {
786 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
791 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
792 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR);
793 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR);
812 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
819 false, rtwdev, R_AX_HALT_C2H_CTRL);
821 rtw89_warn(rtwdev, "Polling FW err status fail\n");
825 err = rtw89_read32(rtwdev, R_AX_HALT_C2H);
826 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
836 if (rtw89_mac_suppress_log(rtwdev, err))
839 rtw89_fw_st_dbg_dump(rtwdev);
840 mac->dump_err_status(rtwdev, err);
846 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)
848 struct rtw89_ser *ser = &rtwdev->ser;
853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err);
858 100000, false, rtwdev, R_AX_HALT_H2C_CTRL);
860 rtw89_err(rtwdev, "FW doesn't receive previous msg\n");
864 rtw89_write32(rtwdev, R_AX_HALT_H2C, err);
870 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
876 static int hfc_reset_param(struct rtw89_dev *rtwdev)
878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
882 switch (rtwdev->hci.type) {
884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode];
907 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch)
909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
926 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev)
928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
933 if (rtwdev->chip->chip_id == RTL8852A)
942 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev)
944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
953 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch)
955 const struct rtw89_chip_info *chip = rtwdev->chip;
957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
962 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
966 ret = hfc_ch_cfg_chk(rtwdev, ch);
976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);
981 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch)
983 const struct rtw89_chip_info *chip = rtwdev->chip;
985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
991 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);
1008 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev)
1010 const struct rtw89_chip_info *chip = rtwdev->chip;
1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg;
1016 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1020 ret = hfc_pub_cfg_chk(rtwdev);
1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);
1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);
1034 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev)
1036 const struct rtw89_chip_info *chip = rtwdev->chip;
1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1044 val = rtw89_read32(rtwdev, regs->pub_page_info1);
1047 val = rtw89_read32(rtwdev, regs->pub_page_info3);
1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2),
1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1),
1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl);
1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);
1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);
1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);
1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);
1089 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev)
1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1095 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1099 mac->hfc_get_mix_info(rtwdev);
1101 ret = hfc_pub_info_chk(rtwdev);
1108 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev)
1110 const struct rtw89_chip_info *chip = rtwdev->chip;
1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl,
1124 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev)
1126 const struct rtw89_chip_info *chip = rtwdev->chip;
1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);
1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);
1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),
1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1159 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
1161 const struct rtw89_chip_info *chip = rtwdev->chip;
1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1175 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en)
1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
1178 const struct rtw89_chip_info *chip = rtwdev->chip;
1184 ret = hfc_reset_param(rtwdev);
1188 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1192 mac->hfc_func_en(rtwdev, false, false);
1195 mac->hfc_h2c_cfg(rtwdev);
1196 mac->hfc_func_en(rtwdev, en, h2c_en);
1203 ret = hfc_ch_ctrl(rtwdev, ch);
1208 ret = hfc_pub_ctrl(rtwdev);
1212 mac->hfc_mix_cfg(rtwdev);
1214 mac->hfc_func_en(rtwdev, en, h2c_en);
1220 ret = hfc_upd_ch_info(rtwdev, ch);
1224 ret = hfc_upd_mix_info(rtwdev);
1230 static int pwr_cmd_poll(struct rtw89_dev *rtwdev,
1239 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr);
1244 rtw89_warn(rtwdev, "[ERR] Polling timeout\n");
1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr);
1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);
1251 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk,
1270 val = rtw89_read8(rtwdev, addr);
1274 rtw89_write8(rtwdev, addr, val);
1277 if (pwr_cmd_poll(rtwdev, cur_cfg))
1294 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev,
1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv),
1310 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev)
1314 switch (rtwdev->ps_mode) {
1331 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev,
1337 spin_lock_bh(&rtwdev->rpwm_lock);
1339 request = rtw89_read16(rtwdev, R_AX_RPWM);
1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) &
1349 rtwdev->mac.rpwm_seq_num);
1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request);
1356 spin_unlock_bh(&rtwdev->rpwm_lock);
1359 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev,
1374 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K))
1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num;
1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr,
1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) &
1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM);
1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num)
1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE);
1406 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter)
1414 state = rtw89_mac_get_req_pwr_state(rtwdev);
1419 rtw89_mac_send_rpwm(rtwdev, state, false);
1422 rtwdev, state);
1427 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n",
1430 rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
1436 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev)
1440 state = rtw89_mac_get_req_pwr_state(rtwdev);
1441 rtw89_mac_send_rpwm(rtwdev, state, true);
1444 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)
1447 const struct rtw89_chip_info *chip = rtwdev->chip;
1449 int (*cfg_func)(struct rtw89_dev *rtwdev);
1461 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
1462 __rtw89_leave_ps_mode(rtwdev);
1464 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);
1466 rtw89_err(rtwdev, "MAC has already powered on\n");
1470 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq);
1475 set_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1476 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
1477 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
1478 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR);
1480 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1481 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
1482 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
1483 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags);
1484 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
1485 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR);
1486 rtw89_set_entity_state(rtwdev, false);
1493 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev)
1495 rtw89_mac_power_switch(rtwdev, false);
1498 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
1521 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1522 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1524 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1527 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en);
1528 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en);
1530 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en);
1531 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en);
1533 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1535 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1537 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1544 static int dmac_func_en_ax(struct rtw89_dev *rtwdev)
1546 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1565 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32);
1573 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32);
1578 static int chip_func_en_ax(struct rtw89_dev *rtwdev)
1580 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1582 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
1583 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
1589 static int sys_init_ax(struct rtw89_dev *rtwdev)
1593 ret = dmac_func_en_ax(rtwdev);
1597 ret = cmac_func_en_ax(rtwdev, 0, true);
1601 ret = chip_func_en_ax(rtwdev);
1689 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,
1692 struct rtw89_mac_info *mac = &rtwdev->mac;
1695 cfg = &rtwdev->chip->dle_mem[mode];
1700 rtw89_warn(rtwdev, "qta mode unmatch!\n");
1714 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev,
1718 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info;
1767 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev)
1773 grpnum = rtwdev->chip->wde_qempty_acq_grpnum;
1778 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
1780 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret);
1792 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel;
1793 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty);
1795 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret);
1802 if (rtwdev->dbcc_en) {
1816 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
1838 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev,
1841 u32 size = rtwdev->chip->fifo_size;
1844 size -= rtwdev->chip->dle_scc_rsvd_size;
1849 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable)
1852 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
1855 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN,
1859 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable)
1864 if (rtwdev->chip->chip_id == RTL8851B)
1866 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val);
1868 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val);
1872 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)
1878 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG);
1892 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");
1899 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val);
1901 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG);
1909 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");
1924 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val);
1929 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple)
1943 2000, false, rtwdev, reg);
1951 rtw89_write32(rtwdev, \
1958 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev,
1973 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev,
1990 if (rtwdev->chip->chip_id == RTL8852C)
1994 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow)
2000 if (rtwdev->chip->chip_id == RTL8852C)
2003 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) {
2004 rtw89_err(rtwdev, "[ERR]support SCC mode only\n");
2009 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW);
2011 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC);
2013 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
2026 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable)
2030 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
2034 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
2036 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
2039 static void dle_quota_cfg(struct rtw89_dev *rtwdev,
2043 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2045 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu);
2046 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt);
2049 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
2052 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2057 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2061 cfg = get_dle_mem_cfg(rtwdev, mode);
2063 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
2069 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode);
2071 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n",
2079 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) {
2080 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
2085 mac->dle_func_en(rtwdev, false);
2086 mac->dle_clk_en(rtwdev, true);
2088 ret = mac->dle_mix_cfg(rtwdev, cfg);
2090 rtw89_err(rtwdev, "[ERR] dle mix cfg\n");
2093 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu);
2095 mac->dle_func_en(rtwdev, true);
2097 ret = mac->chk_dle_rdy(rtwdev, true);
2099 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n");
2103 ret = mac->chk_dle_rdy(rtwdev, false);
2105 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n");
2111 mac->dle_func_en(rtwdev, false);
2112 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n",
2113 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS));
2114 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n",
2115 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS));
2120 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
2129 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size);
2130 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN);
2135 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND);
2136 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size);
2141 static bool is_qta_poh(struct rtw89_dev *rtwdev)
2143 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
2146 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
2149 const struct rtw89_chip_info *chip = rtwdev->chip;
2151 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) ||
2152 !is_qta_poh(rtwdev))
2155 return preload_init_set(rtwdev, mac_idx, mode);
2158 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev)
2176 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
2184 static void _patch_ss2f_path(struct rtw89_dev *rtwdev)
2186 const struct rtw89_chip_info *chip = rtwdev->chip;
2188 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
2191 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK,
2195 static int sta_sch_init_ax(struct rtw89_dev *rtwdev)
2201 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2205 val = rtw89_read8(rtwdev, R_AX_SS_CTRL);
2207 rtw89_write8(rtwdev, R_AX_SS_CTRL, val);
2210 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL);
2212 rtw89_err(rtwdev, "[ERR]STA scheduler init\n");
2216 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG);
2217 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN);
2219 _patch_ss2f_path(rtwdev);
2224 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev)
2228 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2232 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
2233 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
2234 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC,
2236 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);
2241 static int sec_eng_init_ax(struct rtw89_dev *rtwdev)
2243 const struct rtw89_chip_info *chip = rtwdev->chip;
2247 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2251 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL);
2260 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val);
2263 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC);
2267 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val);
2270 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1,
2276 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2280 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
2282 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret);
2286 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode);
2288 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret);
2292 ret = rtw89_mac_hfc_init(rtwdev, true, true, true);
2294 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret);
2298 ret = sta_sch_init_ax(rtwdev);
2300 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret);
2304 ret = mpdu_proc_init_ax(rtwdev);
2306 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret);
2310 ret = sec_eng_init_ax(rtwdev);
2312 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret);
2319 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2325 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2329 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx);
2331 val = rtw89_read32(rtwdev, reg);
2334 rtw89_write32(rtwdev, reg, val);
2337 1, TRXCFG_WAIT_CNT, false, rtwdev, reg);
2339 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n");
2346 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2352 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2356 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx);
2357 if (rtwdev->chip->chip_id == RTL8852C)
2358 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
2361 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
2364 if (rtw89_is_rtl885xb(rtwdev)) {
2365 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx);
2366 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV);
2369 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx);
2370 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN);
2372 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx);
2373 if (rtwdev->chip->chip_id == RTL8852C) {
2374 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
2377 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
2380 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
2387 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev,
2406 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n");
2412 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx);
2415 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx);
2418 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx);
2421 rtw89_err(rtwdev, "[ERR]set rx filter type err\n");
2424 rtw89_write32(rtwdev, reg, val);
2429 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2434 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2439 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST,
2444 mac_ftlr = rtwdev->hal.rx_fltr;
2449 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx),
2451 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx),
2457 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx)
2468 switch (rtwdev->chip->chip_id) {
2471 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx);
2472 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav;
2473 rtw89_write32(rtwdev, reg, val32);
2475 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2476 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca;
2477 rtw89_write32(rtwdev, reg, val32);
2480 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx);
2481 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav;
2482 rtw89_write32(rtwdev, reg, val32);
2484 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2485 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca;
2486 rtw89_write32(rtwdev, reg, val32);
2491 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2496 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2500 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx);
2501 val = rtw89_read32(rtwdev, reg);
2516 rtw89_write32(rtwdev, reg, val);
2518 _patch_dis_resp_chk(rtwdev, mac_idx);
2523 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev)
2525 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN |
2528 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS);
2533 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2538 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2541 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx);
2542 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN);
2544 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx);
2545 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN);
2550 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2555 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2559 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx);
2560 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN);
2562 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx);
2563 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD);
2565 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx);
2566 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE);
2567 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE);
2572 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2574 const struct rtw89_chip_info *chip = rtwdev->chip;
2579 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2583 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2584 val = rtw89_read32(rtwdev, reg);
2588 switch (rtwdev->chip->chip_id) {
2603 rtw89_write32(rtwdev, reg, val);
2605 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx);
2606 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN);
2608 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx);
2609 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
2610 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx);
2611 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);
2616 static void rst_bacam(struct rtw89_dev *rtwdev)
2621 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK,
2626 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK);
2628 rtw89_warn(rtwdev, "failed to reset BA CAM\n");
2631 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2638 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2643 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2648 rst_bacam(rtwdev);
2650 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx);
2651 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL);
2653 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx);
2654 val = rtw89_read16(rtwdev, reg);
2661 rtw89_write16(rtwdev, reg, val);
2663 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx);
2664 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1);
2666 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx);
2668 rx_qta = rtwdev->mac.dle_info.c0_rx_qta;
2670 rx_qta = rtwdev->mac.dle_info.c1_rx_qta;
2672 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size;
2675 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len);
2677 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) {
2678 rtw89_write16_mask(rtwdev,
2679 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx),
2681 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx),
2685 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx);
2686 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK);
2691 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2693 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2697 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2701 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
2702 val = rtw89_read32(rtwdev, reg);
2706 rtw89_write32(rtwdev, reg, val);
2708 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
2709 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx);
2710 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN);
2716 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)
2720 cfg = get_dle_mem_cfg(rtwdev, mode);
2722 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
2729 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2734 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2738 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
2739 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx);
2740 val = rtw89_read32(rtwdev, reg);
2746 rtw89_write32(rtwdev, reg, val);
2748 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx);
2749 val = rtw89_read32(rtwdev, reg);
2752 rtw89_write32(rtwdev, reg, val);
2756 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2758 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2762 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL,
2765 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1,
2772 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2777 if (!rtw89_is_rtl885xb(rtwdev))
2780 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2784 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx);
2785 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE);
2790 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
2794 ret = scheduler_init_ax(rtwdev, mac_idx);
2796 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret);
2800 ret = addr_cam_init_ax(rtwdev, mac_idx);
2802 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx,
2807 ret = rx_fltr_init_ax(rtwdev, mac_idx);
2809 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx,
2814 ret = cca_ctrl_init_ax(rtwdev, mac_idx);
2816 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx,
2821 ret = nav_ctrl_init_ax(rtwdev);
2823 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx,
2828 ret = spatial_reuse_init_ax(rtwdev, mac_idx);
2830 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n",
2835 ret = tmac_init_ax(rtwdev, mac_idx);
2837 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret);
2841 ret = trxptcl_init_ax(rtwdev, mac_idx);
2843 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret);
2847 ret = rmac_init_ax(rtwdev, mac_idx);
2849 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret);
2853 ret = cmac_com_init_ax(rtwdev, mac_idx);
2855 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret);
2859 ret = ptcl_init_ax(rtwdev, mac_idx);
2861 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret);
2865 ret = cmac_dma_init_ax(rtwdev, mac_idx);
2867 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret);
2874 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev,
2877 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2881 mac->cnv_efuse_state(rtwdev, false);
2886 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info);
2894 mac->cnv_efuse_state(rtwdev, true);
2899 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
2901 struct rtw89_efuse *efuse = &rtwdev->efuse;
2902 struct rtw89_hal *hal = &rtwdev->hal;
2903 const struct rtw89_chip_info *chip = rtwdev->chip;
2912 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info);
2943 rtw89_debug(rtwdev, RTW89_DBG_FW,
2947 rtw89_debug(rtwdev, RTW89_DBG_FW,
2950 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity);
2951 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity);
2956 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band,
2971 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
2981 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx,
2984 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx);
2988 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2992 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
2993 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx,
2996 val = rtw89_read16(rtwdev, reg);
2998 rtw89_write16(rtwdev, reg, val);
3003 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
3006 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx);
3010 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
3014 val = rtw89_read32(rtwdev, reg);
3016 rtw89_write32(rtwdev, reg, val);
3021 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
3026 *tx_en = rtw89_read16(rtwdev,
3027 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx));
3031 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
3037 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
3043 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
3049 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
3062 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
3067 *tx_en = rtw89_read32(rtwdev,
3068 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx));
3072 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
3078 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
3084 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
3090 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
3103 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
3107 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK);
3115 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
3119 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en,
3128 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id)
3136 rtw89_write32(rtwdev, reg, val);
3141 1, 2000, false, rtwdev, reg);
3152 static int set_cpuio_ax(struct rtw89_dev *rtwdev,
3166 rtw89_write32(rtwdev, reg, val);
3178 rtw89_write32(rtwdev, reg, val);
3189 rtw89_write32(rtwdev, reg, val);
3194 1, 2000, false, rtwdev, reg);
3205 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
3208 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3211 cfg = get_dle_mem_cfg(rtwdev, mode);
3213 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
3217 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) {
3218 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
3222 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU);
3224 return mac->dle_quota_change(rtwdev, band1_en);
3227 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en)
3229 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3234 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id);
3236 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n");
3246 ret = mac->set_cpuio(rtwdev, &ctrl_para, true);
3248 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n");
3252 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id);
3254 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n");
3264 ret = mac->set_cpuio(rtwdev, &ctrl_para, false);
3266 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n");
3273 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx)
3279 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
3283 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx);
3289 false, rtwdev, reg);
3296 static int band1_enable_ax(struct rtw89_dev *rtwdev)
3303 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL);
3305 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret);
3310 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4);
3311 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4);
3312 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX);
3313 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX);
3316 ret = band_idle_ck_b(rtwdev, 0);
3318 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret);
3322 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true);
3324 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
3329 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]);
3330 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]);
3333 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en);
3335 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret);
3339 ret = cmac_func_en_ax(rtwdev, 1, true);
3341 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret);
3345 ret = cmac_init_ax(rtwdev, 1);
3347 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret);
3351 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
3357 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev)
3359 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3361 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR);
3362 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
3365 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev)
3367 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3369 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
3372 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev)
3374 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3375 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3377 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3384 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3389 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3392 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR,
3396 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR,
3400 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev)
3402 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3404 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
3408 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
3412 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev)
3414 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3416 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
3418 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
3420 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
3422 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
3426 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev)
3428 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3430 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
3431 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
3434 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev)
3436 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3438 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
3439 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
3442 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev)
3444 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR,
3448 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev)
3450 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3452 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
3454 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
3456 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
3458 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
3460 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
3462 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
3466 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev)
3468 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR);
3469 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET);
3472 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev)
3474 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3476 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
3478 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3480 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3482 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
3484 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR);
3487 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3491 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx);
3492 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN |
3494 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN);
3497 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3499 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3502 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx);
3503 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
3504 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
3507 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3509 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3510 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3513 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx);
3514 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
3515 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
3518 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx);
3519 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
3520 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
3524 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3526 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3529 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx);
3530 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
3531 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
3534 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3536 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3539 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx);
3540 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
3541 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
3544 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3546 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3549 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx);
3550 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
3551 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);
3554 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx,
3559 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel);
3561 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n",
3567 rtw89_wdrls_imr_enable(rtwdev);
3568 rtw89_wsec_imr_enable(rtwdev);
3569 rtw89_mpdu_trx_imr_enable(rtwdev);
3570 rtw89_sta_sch_imr_enable(rtwdev);
3571 rtw89_txpktctl_imr_enable(rtwdev);
3572 rtw89_wde_imr_enable(rtwdev);
3573 rtw89_ple_imr_enable(rtwdev);
3574 rtw89_pktin_imr_enable(rtwdev);
3575 rtw89_dispatcher_imr_enable(rtwdev);
3576 rtw89_cpuio_imr_enable(rtwdev);
3577 rtw89_bbrpt_imr_enable(rtwdev);
3579 rtw89_scheduler_imr_enable(rtwdev, mac_idx);
3580 rtw89_ptcl_imr_enable(rtwdev, mac_idx);
3581 rtw89_cdma_imr_enable(rtwdev, mac_idx);
3582 rtw89_phy_intf_imr_enable(rtwdev, mac_idx);
3583 rtw89_rmac_imr_enable(rtwdev, mac_idx);
3584 rtw89_tmac_imr_enable(rtwdev, mac_idx);
3592 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en)
3594 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR,
3596 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR,
3598 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta)
3599 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1,
3603 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable)
3608 ret = band1_enable_ax(rtwdev);
3610 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret);
3614 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL);
3616 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret);
3620 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n");
3627 static int set_host_rpr_ax(struct rtw89_dev *rtwdev)
3629 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
3630 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3632 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0,
3635 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3637 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0,
3641 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30);
3642 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255);
3647 static int trx_init_ax(struct rtw89_dev *rtwdev)
3649 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3650 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;
3653 ret = dmac_init_ax(rtwdev, 0);
3655 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret);
3659 ret = cmac_init_ax(rtwdev, 0);
3661 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret);
3665 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) {
3666 ret = dbcc_enable_ax(rtwdev, true);
3668 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret);
3673 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
3675 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret);
3679 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
3681 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret);
3685 err_imr_ctrl_ax(rtwdev, true);
3687 ret = set_host_rpr_ax(rtwdev);
3689 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret);
3694 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG,
3700 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev)
3705 const struct rtw89_chip_info *chip = rtwdev->chip;
3713 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0);
3717 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1);
3722 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev)
3726 if (rtw89_is_rtl885xb(rtwdev)) {
3727 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);
3728 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);
3732 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL,
3735 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL);
3738 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL);
3741 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev)
3743 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
3745 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3746 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN |
3748 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3750 rtw89_disable_fw_watchdog(rtwdev);
3752 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3753 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3756 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason,
3762 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN)
3765 rtw89_write32(rtwdev, R_AX_UDM1, 0);
3766 rtw89_write32(rtwdev, R_AX_UDM2, 0);
3767 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0);
3768 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
3769 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0);
3770 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0);
3772 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3774 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL);
3782 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val);
3784 if (rtwdev->chip->chip_id == RTL8852B)
3785 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL,
3788 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK,
3790 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3795 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE);
3803 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev)
3805 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3814 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val);
3817 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev)
3819 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3826 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val);
3831 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1);
3835 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val);
3837 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1,
3842 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11);
3843 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN);
3846 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev)
3848 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3851 mac->hci_func_en(rtwdev);
3852 mac->dmac_func_pre_en(rtwdev);
3854 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode);
3856 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret);
3860 ret = rtw89_mac_hfc_init(rtwdev, true, false, true);
3862 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret);
3869 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
3871 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
3873 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL,
3876 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3882 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
3884 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
3886 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL,
3889 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3895 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb)
3899 ret = rtw89_mac_power_switch(rtwdev, true);
3901 rtw89_mac_power_switch(rtwdev, false);
3902 ret = rtw89_mac_power_switch(rtwdev, true);
3907 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true);
3910 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0);
3911 if (rtwdev->dbcc_en)
3912 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1);
3915 ret = rtw89_mac_dmac_pre_init(rtwdev);
3919 if (rtwdev->hci.ops->mac_pre_init) {
3920 ret = rtwdev->hci.ops->mac_pre_init(rtwdev);
3925 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb);
3932 int rtw89_mac_init(struct rtw89_dev *rtwdev)
3934 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
3935 const struct rtw89_chip_info *chip = rtwdev->chip;
3939 ret = rtw89_mac_partial_init(rtwdev, include_bb);
3943 ret = rtw89_chip_enable_bb_rf(rtwdev);
3947 ret = mac->sys_init(rtwdev);
3951 ret = mac->trx_init(rtwdev);
3955 ret = rtw89_mac_feat_init(rtwdev);
3959 if (rtwdev->hci.ops->mac_post_init) {
3960 ret = rtwdev->hci.ops->mac_post_init(rtwdev);
3965 rtw89_fw_send_all_early_h2c(rtwdev);
3966 rtw89_fw_h2c_set_ofld_cfg(rtwdev);
3970 rtw89_mac_power_switch(rtwdev, false);
3975 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
3979 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
3983 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
3985 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0);
3989 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
3991 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
3994 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
3996 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4);
3997 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004);
3998 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0);
3999 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0);
4000 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0);
4001 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B);
4002 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0);
4003 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109);
4006 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause)
4015 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) &&
4016 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4019 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
4023 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause);
4057 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev,
4060 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4067 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif->mac_idx);
4068 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif->mac_idx);
4070 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type);
4071 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN);
4075 true, rtwdev, reg_info, mask);
4077 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n");
4080 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4082 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4085 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif->port));
4086 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 1);
4087 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 0);
4088 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 0);
4089 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 2);
4090 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK, 1);
4091 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 1);
4092 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
4094 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM0);
4096 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM1);
4098 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif->port));
4099 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TBTT_PROHIB_EN);
4112 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev,
4115 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4118 const struct rtw89_chip_info *chip = rtwdev->chip;
4122 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN))
4127 backup_val = rtw89_read32_port(rtwdev, rtwvif, p->tbtt_prohib);
4131 rtw89_mac_bcn_drop(rtwdev, rtwvif);
4134 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK);
4135 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1);
4136 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK);
4137 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK);
4141 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN |
4143 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST);
4144 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0);
4147 rtw89_write32_port(rtwdev, rtwvif, p->tbtt_prohib, backup_val);
4150 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev,
4153 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4157 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
4159 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
4162 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev,
4165 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4169 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
4171 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
4174 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev,
4177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4180 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK,
4184 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev,
4187 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4193 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits);
4195 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits);
4198 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev,
4201 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4208 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit);
4210 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit);
4213 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
4216 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4220 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
4222 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
4225 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev,
4231 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif, en);
4234 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev,
4237 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4241 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
4243 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
4246 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev,
4252 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en);
4255 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en)
4259 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4261 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en);
4264 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev,
4267 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4272 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK,
4276 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev,
4280 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4285 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx);
4286 rtw89_write8(rtwdev, reg, win);
4289 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev,
4292 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4297 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx);
4298 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE);
4300 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK,
4304 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev,
4307 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4310 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
4314 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev,
4317 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4320 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
4324 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev,
4327 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4330 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area,
4334 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev,
4337 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4340 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early,
4344 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev,
4347 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4362 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx);
4363 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color);
4366 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev,
4369 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4378 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx);
4379 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK);
4383 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev,
4386 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4392 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx);
4393 val = rtw89_read32(rtwdev, reg);
4397 rtw89_write32(rtwdev, reg, val);
4400 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev,
4403 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4407 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg,
4410 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg,
4414 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev,
4417 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4420 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK,
4424 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev,
4427 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4431 if (rtwdev->chip->chip_id != RTL8852C)
4441 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift,
4445 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
4450 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4455 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4,
4458 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port);
4459 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val);
4460 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW);
4463 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev,
4473 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src,
4479 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev)
4485 rtw89_for_each_rtwvif(rtwdev, tmp) {
4497 rtw89_for_each_rtwvif(rtwdev, tmp)
4498 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset);
4501 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4505 ret = rtw89_mac_port_update(rtwdev, rtwvif);
4509 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id);
4510 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id);
4512 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false);
4516 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE);
4520 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true);
4524 ret = rtw89_cam_init(rtwdev, rtwvif);
4528 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
4532 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, NULL);
4536 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, NULL);
4543 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4547 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE);
4551 rtw89_cam_deinit(rtwdev, rtwvif);
4553 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
4560 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4567 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif);
4568 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false);
4569 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false);
4570 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif);
4571 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif);
4572 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif);
4573 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif);
4574 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif);
4575 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif);
4576 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif);
4577 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif);
4578 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif);
4579 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif);
4580 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif);
4581 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif);
4582 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif);
4583 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif);
4584 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif);
4585 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif);
4586 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true);
4587 rtw89_mac_port_tsf_resync_all(rtwdev);
4589 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif);
4594 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4597 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4602 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL);
4606 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l);
4607 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h);
4632 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
4636 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4637 struct ieee80211_hw *hw = rtwdev->hw;
4651 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr,
4654 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask);
4656 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask);
4659 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4661 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif);
4664 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4668 rtwvif->mac_id = rtw89_acquire_mac_id(rtwdev);
4672 ret = rtw89_mac_vif_init(rtwdev, rtwvif);
4679 rtw89_release_mac_id(rtwdev, rtwvif->mac_id);
4684 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4688 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif);
4689 rtw89_release_mac_id(rtwdev, rtwvif->mac_id);
4695 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4699 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel)
4701 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
4707 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4712 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
4716 u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf;
4733 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))
4736 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN,
4740 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
4746 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN,
4754 if (rtw89_is_op_chan(rtwdev, band, chan)) {
4755 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false);
4756 ieee80211_stop_queues(rtwdev->hw);
4760 if (rtwdev->scan_info.abort)
4765 ret = rtw89_hw_scan_offload(rtwdev, vif, true);
4767 rtw89_hw_scan_abort(rtwdev, vif);
4768 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret);
4771 rtw89_hw_scan_complete(rtwdev, vif, false);
4776 if (rtw89_is_op_chan(rtwdev, band, chan)) {
4777 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx,
4778 &rtwdev->scan_info.op_chan);
4779 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true);
4780 ieee80211_wake_queues(rtwdev->hw);
4784 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx,
4794 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4812 rtw89_debug(rtwdev, RTW89_DBG_FW,
4818 if (!rtwdev->scanning && !rtwvif->offchan)
4821 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true);
4842 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
4847 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4848 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h);
4852 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4856 rtw89_debug(rtwdev, RTW89_DBG_FW,
4865 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len)
4868 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
4879 rtw89_debug(rtwdev, RTW89_DBG_FW,
4911 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4913 rtw89_fw_log_dump(rtwdev, c2h->data, len);
4917 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4922 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h,
4925 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
4934 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n",
4944 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
4947 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE);
4951 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4968 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4973 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4978 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5001 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5006 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5015 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5019 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5034 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5046 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5050 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5102 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5107 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5121 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
5125 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5127 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
5145 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5159 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len)
5161 struct rtw89_wow_param *rtw_wow = &rtwdev->wow;
5163 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
5190 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
5192 struct rtw89_wait_info *wait = &rtwdev->mcc.wait;
5222 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5226 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5230 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5234 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5238 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5242 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5246 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5250 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5254 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5258 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5262 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5267 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
5284 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,
5297 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev,
5306 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev,
5315 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev,
5322 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev,
5327 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev,
5332 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
5342 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
5351 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
5370 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h);
5384 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
5387 void (*handler)(struct rtw89_dev *rtwdev,
5414 rtw89_info(rtwdev, "c2h class %d not support\n", class);
5418 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class,
5422 handler(rtwdev, skb, len);
5426 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev,
5430 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode;
5431 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx);
5434 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n",
5441 rtw89_err(rtwdev,
5451 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n",
5458 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
5460 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx);
5463 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5468 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN);
5472 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN |
5476 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK,
5482 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx)
5490 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
5491 struct ieee80211_hw *hw = rtwdev->hw;
5507 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx);
5508 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th);
5509 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th);
5512 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop)
5517 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5521 10000, 200000, false, rtwdev);
5522 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning))
5523 rtw89_info(rtwdev, "timed out to flush queues\n");
5526 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex)
5528 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
5534 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT);
5536 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN);
5537 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8);
5538 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK);
5539 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16);
5541 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24);
5543 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0);
5545 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16);
5547 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32);
5549 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n");
5553 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32);
5555 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n");
5561 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
5564 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
5566 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE);
5567 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);
5569 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5);
5572 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val);
5575 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
5578 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
5580 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE);
5588 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16);
5590 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE);
5598 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
5600 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
5603 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
5605 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
5608 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
5610 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
5620 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
5623 rtw89_write32_set(rtwdev, R_AX_BTC_CFG,
5625 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN);
5626 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN);
5627 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN);
5631 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
5633 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1,
5637 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
5648 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
5677 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val);
5679 rtw89_err(rtwdev, "Write LTE fail!\n");
5687 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
5728 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val);
5735 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
5741 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);
5745 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band);
5755 rtw89_write16(rtwdev, reg, val);
5760 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)
5764 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD);
5767 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5775 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val);
5779 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev)
5781 return rtw89_read32(rtwdev, R_AX_SCOREBOARD);
5784 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
5786 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);
5789 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val);
5795 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl)
5797 struct rtw89_btc *btc = &rtwdev->btc;
5812 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt);
5816 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev)
5818 const struct rtw89_chip_info *chip = rtwdev->chip;
5823 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
5824 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3,
5830 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band)
5835 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band);
5836 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK);
5837 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST);
5842 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx,
5847 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
5850 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep);
5851 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);
5853 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
5854 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,
5857 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
5858 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,
5863 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
5865 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
5869 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en);
5870 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx);
5872 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
5873 rtw89_write32_set(rtwdev, reg, mask);
5875 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
5876 rtw89_write32_clr(rtwdev, reg, mask);
5880 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx)
5886 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5892 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx);
5893 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN);
5895 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx);
5896 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP);
5898 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);
5900 rtw89_write32(rtwdev, reg, val32);
5901 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true);
5902 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);
5904 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
5905 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL |
5909 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx);
5910 rtw89_write32(rtwdev, reg,
5915 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx);
5916 rtw89_write32_set(rtwdev, reg,
5922 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev,
5936 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5959 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
5960 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
5971 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
5973 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx);
5975 rtw89_write16(rtwdev, reg, val);
5980 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev,
5990 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6009 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
6010 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
6011 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN);
6012 rtw89_write32(rtwdev,
6013 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx),
6019 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev,
6026 rtw89_debug(rtwdev, RTW89_DBG_BF,
6028 rtw89_mac_init_bfee_ax(rtwdev, rtwvif->mac_idx);
6029 rtw89_mac_set_csi_para_reg_ax(rtwdev, vif, sta);
6030 rtw89_mac_csi_rrsc_ax(rtwdev, vif, sta);
6034 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
6039 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false);
6042 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
6049 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n");
6052 rtw89_write32(rtwdev,
6053 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx),
6055 rtw89_write32(rtwdev,
6056 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx),
6060 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx),
6062 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx),
6064 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx),
6066 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx),
6071 struct rtw89_dev *rtwdev;
6091 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
6096 data.rtwdev = rtwdev;
6099 ieee80211_iterate_stations_atomic(rtwdev->hw,
6103 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count);
6105 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
6107 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
6110 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
6112 struct rtw89_traffic_stats *stats = &rtwdev->stats;
6115 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
6119 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
6125 rtw89_for_each_rtwvif(rtwdev, rtwvif)
6126 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx,
6133 rtw89_for_each_rtwvif(rtwdev, rtwvif)
6134 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en);
6138 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
6149 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
6151 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6153 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n");
6157 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx);
6158 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK,
6165 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
6172 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);
6174 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);
6181 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
6191 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6193 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n");
6197 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx);
6198 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5;
6204 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
6214 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
6216 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
6223 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
6233 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6235 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n");
6239 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx);
6240 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK);
6246 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
6249 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6255 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
6259 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx);
6261 rtw89_write16_set(rtwdev, reg, set);
6263 rtw89_write16_clr(rtwdev, reg, set);
6269 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
6279 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
6282 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
6284 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
6293 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
6303 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
6306 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
6308 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);
6312 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1);
6318 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)
6338 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms);
6346 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
6352 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta);
6355 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
6357 ieee80211_iterate_stations_atomic(rtwdev->hw,
6362 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
6365 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6375 50000, false, rtwdev);
6376 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw))
6377 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms);
6384 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable)
6394 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
6404 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow)
6406 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6407 const struct rtw89_chip_info *chip = rtwdev->chip;
6411 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true);
6413 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
6417 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
6418 rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
6419 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE);
6420 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
6421 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0);
6422 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0);
6423 rtw89_write32(rtwdev, R_AX_TF_FWD, 0);
6424 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0);
6426 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
6427 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY);
6429 rtw89_write32_set(rtwdev, R_AX_DBG_WOW,
6432 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false);
6434 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret);
6438 rtw89_mac_cpu_io_rx(rtwdev, enable_wow);
6439 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP);
6440 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
6441 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
6442 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
6448 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type)
6450 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL);
6456 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev,
6464 rtwdev, R_AX_WCPU_FW_CTRL);