Lines Matching +full:emem +full:- +full:configuration
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
29 ether_addr_copy(efuse->addr, map->e.mac_addr);
35 ether_addr_copy(efuse->addr, map->u.mac_addr);
41 ether_addr_copy(efuse->addr, map->s.mac_addr);
46 struct rtw_efuse *efuse = &rtwdev->efuse;
52 efuse->rfe_option = map->rfe_option;
53 efuse->rf_board_option = map->rf_board_option;
54 efuse->crystal_cap = map->xtal_k & XCAP_MASK;
55 efuse->channel_plan = map->channel_plan;
56 efuse->country_code[0] = map->country_code[0];
57 efuse->country_code[1] = map->country_code[1];
58 efuse->bt_setting = map->rf_bt_setting;
59 efuse->regd = map->rf_board_option & 0x7;
60 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal;
61 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal;
62 efuse->thermal_meter_k =
63 (map->path_a_thermal + map->path_b_thermal) >> 1;
64 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf;
67 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
81 return -ENOTSUPP;
201 for (i = 0; i < DACK_SN_8822C - 1; i++) {
202 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) {
215 for (i = 10; i < DACK_SN_8822C - 10; i++) {
217 m = (0x400 - vec[i]) + m;
223 t = p - m;
224 t = t / (DACK_SN_8822C - 20);
226 t = m - p;
227 t = t / (DACK_SN_8822C - 20);
229 t = 0x400 - t;
248 return -1;
267 return -1;
277 if ((value >= 0x200 && (0x400 - value) > 0x64) ||
323 i_delta = i_max - i_min;
325 i_delta = i_max - i_min;
327 i_delta = i_max + (0x400 - i_min);
330 q_delta = q_max - q_min;
332 q_delta = q_max - q_min;
334 q_delta = q_max + (0x400 - q_min);
350 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12;
351 qv[DACK_SN_8822C - 1] = temp & 0x3ff;
370 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
371 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
396 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
437 ic = 0x400 - ic;
441 qc = 0x400 - qc;
446 dm_info->dack_adck[path] = temp;
455 ic = 0x400 - ic;
457 qc = 0x400 - qc;
473 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
480 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
540 ic = 0x400 - ic;
542 qc = 0x400 - qc;
547 ic = (0x400 - ic) * 2 * 6 / 5;
548 ic = 0x7f - ic;
554 qc = (0x400 - qc) * 2 * 6 / 5;
555 qc = 0x7f - qc;
618 ic = ic - 0x10;
620 ic = 0x400 - (0x10 - ic);
623 qc = qc - 0x10;
625 qc = 0x400 - (0x10 - qc);
631 ic = 0x400 - ic;
633 qc = 0x400 - qc;
655 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
665 dm_info->dack_msbk[path][vec][i] = val;
691 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
695 dm_info->dack_dck[RF_PATH_A][0][0] = val;
697 dm_info->dack_dck[RF_PATH_A][0][1] = val;
699 dm_info->dack_dck[RF_PATH_A][1][0] = val;
701 dm_info->dack_dck[RF_PATH_A][1][1] = val;
704 dm_info->dack_dck[RF_PATH_B][0][0] = val;
706 dm_info->dack_dck[RF_PATH_B][1][0] = val;
708 dm_info->dack_dck[RF_PATH_B][0][1] = val;
710 dm_info->dack_dck[RF_PATH_B][1][1] = val;
724 /* backup path-A I/Q */
729 /* backup path-B I/Q */
745 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
749 val = dm_info->dack_dck[RF_PATH_A][0][0];
751 val = dm_info->dack_dck[RF_PATH_A][0][1];
755 val = dm_info->dack_dck[RF_PATH_A][1][0];
757 val = dm_info->dack_dck[RF_PATH_A][1][1];
761 val = dm_info->dack_dck[RF_PATH_B][0][0];
763 val = dm_info->dack_dck[RF_PATH_B][0][1];
767 val = dm_info->dack_dck[RF_PATH_B][1][0];
769 val = dm_info->dack_dck[RF_PATH_B][1][1];
845 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
862 value = dm_info->dack_msbk[path][0][i];
875 value = dm_info->dack_msbk[path][1][i];
903 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
907 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 &&
908 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 &&
909 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 &&
910 dm_info->dack_msbk[RF_PATH_B][1][0] == 0)
960 /* path-A */
976 /* path-B */
1033 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1076 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1116 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1124 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1134 struct rtw_dm_info *dm = &rtwdev->dm_info;
1143 if (!dm->is_bt_iqk_timeout) {
1151 dm->is_bt_iqk_timeout = true;
1183 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1400 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1427 v = txgapk->rf3f_bp[band][gain][path];
1430 tmp_3f = txgapk->rf3f_bp[band][gain][path];
1435 txgapk->rf3f_bp[band][gain][path]);
1437 tmp_3f = txgapk->rf3f_bp[band][gain][path];
1456 __func__, rtwdev->dm_info.gapk.channel);
1459 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1472 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1473 u8 channel = txgapk->channel;
1518 txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1519 txgapk->offset[1][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val);
1520 txgapk->offset[2][path] = (s8)FIELD_GET(BIT_GAPK_RPT2, val);
1521 txgapk->offset[3][path] = (s8)FIELD_GET(BIT_GAPK_RPT3, val);
1522 txgapk->offset[4][path] = (s8)FIELD_GET(BIT_GAPK_RPT4, val);
1523 txgapk->offset[5][path] = (s8)FIELD_GET(BIT_GAPK_RPT5, val);
1524 txgapk->offset[6][path] = (s8)FIELD_GET(BIT_GAPK_RPT6, val);
1525 txgapk->offset[7][path] = (s8)FIELD_GET(BIT_GAPK_RPT7, val);
1530 txgapk->offset[8][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1531 txgapk->offset[9][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val);
1534 if (txgapk->offset[i][path] & BIT(3))
1535 txgapk->offset[i][path] = txgapk->offset[i][path] |
1540 txgapk->offset[i][path], i, path);
1547 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1548 u8 channel = txgapk->channel;
1621 if (path >= rtwdev->hal.rf_path_num)
1655 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1658 u8 path, band = RF_BAND_2G_OFDM, channel = txgapk->channel;
1679 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1683 v = txgapk->rf3f_bp[band][j][path];
1687 offset_tmp[i] += txgapk->offset[j][path];
1688 txgapk->fianl_offset[i][path] = offset_tmp[i];
1691 v = txgapk->rf3f_bp[band][i][path];
1695 txgapk->rf3f_bp[band][i][path]);
1697 txgapk->rf3f_fs[path][i] = offset_tmp[i];
1710 txgapk->rf3f_bp[band][i][path],
1725 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1733 if (rtwdev->dm_info.dm_flags & BIT(RTW_DM_CAP_TXGAPK))
1738 if (txgapk->read_txgain == 1) {
1740 "[TXGAPK] Already Read txgapk->read_txgain return!!!\n");
1746 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1765 txgapk->rf3f_bp[band][gain][path] = v & BIT_DATA_L;
1769 txgapk->rf3f_bp[band][gain][path],
1779 txgapk->read_txgain = 1;
1785 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1793 if (txgapk->read_txgain == 0) {
1795 "[TXGAPK] txgapk->read_txgain == 0 return!!!\n");
1799 if (rtwdev->efuse.power_track_type >= 4 &&
1800 rtwdev->efuse.power_track_type <= 7) {
1809 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1810 txgapk->channel = rtw_read_rf(rtwdev, path,
1826 struct rtw_dm_info *dm = &rtwdev->dm_info;
1828 if (dm->dm_flags & BIT(RTW_DM_CAP_TXGAPK)) {
1848 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1852 dm_info->delta_power_index[path] = 0;
1853 ewma_thermal_init(&dm_info->avg_thermal[path]);
1854 dm_info->thermal_avg[path] = 0xff;
1857 dm_info->pwr_trk_triggered = false;
1858 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
1859 dm_info->thermal_meter_lck = rtwdev->efuse.thermal_meter_k;
1864 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1865 struct rtw_hal *hal = &rtwdev->hal;
1888 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1896 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
1905 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb));
1906 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb));
2034 /* protocol configuration */
2054 /* EDCA configuration */
2065 /* MAC clock configuration */
2077 /* Set beacon cotnrol - enable TSF and other related functions */
2086 /* WMAC configuration */
2117 /* rx ignore configuration */
2126 /* Interrupt migration configuration */
2167 ret = __dump_fw_8822c(rtwdev, EMEM);
2265 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
2266 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
2554 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2558 s8 min_rx_power = -120;
2565 l_bnd = dm_info->cck_gi_l_bnd;
2566 u_bnd = dm_info->cck_gi_u_bnd;
2570 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1;
2572 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1;
2574 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1;
2576 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1;
2578 rx_power[RF_PATH_A] -= 110;
2579 rx_power[RF_PATH_B] -= 110;
2583 channel = rtwdev->hal.current_channel;
2586 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A];
2587 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B];
2589 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2590 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
2591 dm_info->rssi[path] = rssi;
2594 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
2595 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
2596 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
2603 struct rtw_path_div *p_div = &rtwdev->dm_path_div;
2604 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2606 s8 min_rx_power = -120;
2613 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
2628 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
2629 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
2630 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
2631 pkt_stat->bw = bw;
2632 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
2633 pkt_stat->rx_power[RF_PATH_B],
2636 dm_info->curr_rx_rate = pkt_stat->rate;
2638 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
2639 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status);
2641 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
2642 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status);
2644 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
2645 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status);
2647 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2648 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
2649 dm_info->rssi[path] = rssi;
2651 p_div->path_a_sum += rssi;
2652 p_div->path_a_cnt++;
2654 p_div->path_b_sum += rssi;
2655 p_div->path_b_cnt++;
2657 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
2658 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
2660 rx_evm = pkt_stat->rx_evm[path];
2666 evm_dbm = ((u8)-rx_evm >> 1);
2668 dm_info->rx_evm_dbm[path] = evm_dbm;
2698 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
2703 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
2704 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
2705 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
2706 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
2708 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
2709 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
2710 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
2711 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
2712 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
2713 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
2714 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
2715 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
2717 /* drv_info_sz is in unit of 8-bytes */
2718 pkt_stat->drv_info_sz *= 8;
2721 if (pkt_stat->is_c2h)
2724 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
2725 pkt_stat->drv_info_sz);
2726 pkt_stat->hdr = hdr;
2727 if (pkt_stat->phy_status) {
2728 phy_status = rx_desc + desc_sz + pkt_stat->shift;
2739 struct rtw_hal *hal = &rtwdev->hal;
2744 for (path = 0; path < hal->rf_path_num; path++) {
2749 for (path = 0; path < hal->rf_path_num; path++) {
2780 struct rtw_hal *hal = &rtwdev->hal;
2782 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M],
2783 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]};
2784 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7],
2785 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]};
2794 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate];
2795 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate];
2797 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0];
2798 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1];
2800 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0];
2801 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1];
2805 rtw8822c_set_tx_power_diff(rtwdev, rate - 3,
2815 struct rtw_hal *hal = &rtwdev->hal;
2824 return -EINVAL;
2834 return -EINVAL;
2837 hal->antenna_tx = antenna_tx;
2838 hal->antenna_rx = antenna_rx;
2856 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2887 dm_info->cck_fa_cnt = cck_fa_cnt;
2888 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
2889 dm_info->total_fa_cnt = ofdm_fa_cnt;
2890 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
2893 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
2894 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2896 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
2897 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2899 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
2900 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2902 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
2903 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2906 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
2907 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
2908 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
2910 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
2974 /* enable PTA (3-wire function form BT side) */
2993 struct rtw_coex *coex = &rtwdev->coex;
2994 struct rtw_coex_stat *coex_stat = &coex->stat;
2995 struct rtw_efuse *efuse = &rtwdev->efuse;
2998 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode)
3001 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode;
3003 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun)
3008 /* BT at S1 for Shared-Ant */
3009 if (efuse->share_ant)
3014 /* WL-S0 2G RF TRX cannot be masked by GNT_BT
3015 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type
3018 * enable "DAC off if GNT_WL = 0" for non-shared-antenna
3022 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) {
3034 /* disable WL-S1 BB chage RF mode if GNT_BT
3040 /* disable WL-S0 BB chage RF mode if wifi is at 5G,
3043 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) {
3048 } else if (coex_stat->wl_coex_mode == COEX_WLINK_5G ||
3049 coex->under_5g || !efuse->share_ant) {
3050 if (coex_stat->kt_ver >= 3) {
3060 /* shared-antenna */
3063 if (coex_stat->kt_ver >= 3) {
3081 struct rtw_coex *coex = &rtwdev->coex;
3082 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
3083 struct rtw_efuse *efuse = &rtwdev->efuse;
3085 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
3086 coex_rfe->ant_switch_polarity = 0;
3087 coex_rfe->ant_switch_exist = false;
3088 coex_rfe->ant_switch_with_bt = false;
3089 coex_rfe->ant_switch_diversity = false;
3091 if (efuse->share_ant)
3092 coex_rfe->wlg_at_btg = true;
3094 coex_rfe->wlg_at_btg = false;
3104 struct rtw_coex *coex = &rtwdev->coex;
3105 struct rtw_coex_dm *coex_dm = &coex->dm;
3107 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
3110 coex_dm->cur_wl_pwr_lvl = wl_pwr;
3115 struct rtw_coex *coex = &rtwdev->coex;
3116 struct rtw_coex_dm *coex_dm = &coex->dm;
3118 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
3121 coex_dm->cur_wl_rx_low_gain_en = low_gain;
3123 if (coex_dm->cur_wl_rx_low_gain_en) {
3124 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
3133 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
3155 if (vif->net_type == RTW_NET_AP_MODE)
3186 if (bfee->role == RTW_BFEE_SU)
3188 else if (bfee->role == RTW_BFEE_MU)
3203 const struct dpk_cfg_pair *p = tbl->data;
3204 const struct dpk_cfg_pair *end = p + tbl->size / 3;
3209 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data);
3214 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3217 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
3218 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
3223 dpk_info->gnt_value);
3224 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
3280 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3291 dpk_info->dpk_band = 1 << band_shift;
3292 dpk_info->dpk_ch = FIELD_GET(0xff, reg);
3293 dpk_info->dpk_bw = FIELD_GET(0x3000, reg);
3315 dc_i = 0x1000 - dc_i;
3317 dc_q = 0x1000 - dc_q;
3364 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3367 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)
3391 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {
3405 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80)
3420 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
3456 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
3469 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
3519 i_val = 0x10000 - i_val;
3521 q_val = 0x10000 - q_val;
3545 tindex = ARRAY_SIZE(table_fraction) - 1;
3549 result = val_integerd_b * 100 - val_fractiond_b;
3593 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870;
3618 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN,
3620 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC,
3623 if (data->loss_only) {
3628 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path,
3629 data->limited_pga);
3630 if (state == RTW_DPK_GAIN_CHECK && data->gain_only)
3636 data->agc_cnt++;
3637 if (data->agc_cnt >= 6)
3646 u8 pga = data->pga;
3649 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3651 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
3653 data->limited_pga = 1;
3661 u8 pga = data->pga;
3664 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3666 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3668 data->limited_pga = 1;
3678 if (data->txbb == txbb_bound[is_large])
3682 data->txbb -= 2;
3684 data->txbb += 3;
3686 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb);
3687 data->limited_pga = 0;
3707 u8 path = data->path;
3763 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1;
3779 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3785 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev);
3806 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3811 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]);
3812 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]);
3824 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3839 coef = dpk_info->coef[path][addr];
3848 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3853 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6));
3857 dpk_info->result[path] = result;
3858 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC);
3865 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3888 tx_bb = tx_bb - tx_agc_search;
3892 tx_agc = ori_txagc - (ori_txbb - tx_bb);
3896 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1);
3920 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3941 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) {
3985 dpk_info->dpk_gs[path] = tmp_gs;
3990 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4005 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4006 i_scaling = 0x16c00 / dpk_info->dpk_gs[path];
4023 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4030 if (test_bit(path, dpk_info->dpk_path_ok))
4055 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4058 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4059 clear_bit(path, dpk_info->dpk_path_ok);
4064 dpk_info->dpk_txagc[path] = 0;
4065 dpk_info->result[path] = 0;
4066 dpk_info->dpk_gs[path] = 0x5b;
4067 dpk_info->pre_pwsf[path] = 0;
4068 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev,
4075 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4090 if (dpk_info->result[path])
4091 set_bit(path, dpk_info->dpk_path_ok);
4105 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4111 dpk_info->is_dpk_pwr_on);
4113 dpk_info->is_dpk_pwr_on);
4115 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) {
4117 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]);
4119 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) {
4121 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]);
4127 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4130 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) &&
4131 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) &&
4132 dpk_info->dpk_ch == 0)
4135 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4138 if (dpk_info->dpk_band == RTW_BAND_2G)
4143 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);
4146 test_bit(path, dpk_info->dpk_path_ok));
4154 dpk_info->dpk_gs[path]);
4157 dpk_info->dpk_gs[path]);
4164 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4167 dpk_info->is_reload = false;
4175 if (channel == dpk_info->dpk_ch) {
4177 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch);
4179 dpk_info->is_reload = true;
4182 return dpk_info->is_reload;
4187 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4198 if (!dpk_info->is_dpk_pwr_on) {
4206 ewma_thermal_init(&dpk_info->avg_thermal[path]);
4222 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
4238 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4243 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0)
4248 ewma_thermal_add(&dpk_info->avg_thermal[path],
4251 ewma_thermal_read(&dpk_info->avg_thermal[path]);
4252 delta_dpk[path] = dpk_info->thermal_dpk[path] -
4254 offset[path] = delta_dpk[path] -
4255 dpk_info->thermal_dpk_delta[path];
4258 if (offset[path] != dpk_info->pre_pwsf[path]) {
4263 dpk_info->pre_pwsf[path] = offset[path];
4271 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4272 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4276 cfo->crystal_cap = crystal_cap;
4282 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4283 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4285 if (cfo->crystal_cap == crystal_cap)
4293 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4294 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4296 cfo->is_adjust = true;
4298 if (cfo->crystal_cap > rtwdev->efuse.crystal_cap)
4299 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap - 1);
4300 else if (cfo->crystal_cap < rtwdev->efuse.crystal_cap)
4301 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap + 1);
4306 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4307 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4309 cfo->crystal_cap = rtwdev->efuse.crystal_cap;
4310 cfo->is_adjust = true;
4316 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4317 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4322 cfo_rpt_sum = REPORT_TO_KHZ(cfo->cfo_tail[i]);
4324 if (cfo->cfo_cnt[i])
4325 cfo_avg = cfo_rpt_sum / cfo->cfo_cnt[i];
4333 cfo->cfo_tail[i] = 0;
4334 cfo->cfo_cnt[i] = 0;
4342 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4343 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4345 if (!cfo->is_adjust) {
4347 cfo->is_adjust = true;
4350 cfo->is_adjust = false;
4354 cfo->is_adjust = false;
4355 rtw8822c_set_crystal_cap(rtwdev, rtwdev->efuse.crystal_cap);
4361 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4362 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
4363 u8 path_num = rtwdev->hal.rf_path_num;
4364 s8 crystal_cap = cfo->crystal_cap;
4367 if (rtwdev->sta_cnt != 1) {
4372 if (cfo->packet_count == cfo->packet_count_pre)
4375 cfo->packet_count_pre = cfo->packet_count;
4379 if (cfo->is_adjust) {
4382 else if (cfo_avg < -CFO_TRK_ADJ_TH)
4383 crystal_cap--;
4445 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4454 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d) bw=%d nr=%d cck_fa_avg=%d\n",
4455 dm_info->cck_pd_lv[bw][nrx], new_lvl, bw, nrx,
4456 dm_info->cck_fa_avg);
4458 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl)
4461 cur_lvl = dm_info->cck_pd_lv[bw][nrx];
4464 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
4467 pd_lvl[new_lvl] - pd_lvl[cur_lvl],
4468 cs_lvl[new_lvl] - cs_lvl[cur_lvl],
4470 dm_info->cck_pd_lv[bw][nrx] = new_lvl;
4476 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4481 dm_info->delta_power_index[rf_path]);
4485 dm_info->delta_power_index[rf_path]);
4496 if (rtwdev->efuse.thermal_meter[path] == 0xff)
4507 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4511 dm_info->delta_power_index[path] =
4524 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4528 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4534 struct rtw_efuse *efuse = &rtwdev->efuse;
4535 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4537 if (efuse->power_track_type != 0)
4540 if (!dm_info->pwr_trk_triggered) {
4549 dm_info->pwr_trk_triggered = true;
4554 dm_info->pwr_trk_triggered = false;
4571 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4575 igi = dm_info->igi_history[0];
4576 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) {
4578 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL;
4580 if (igi < dm_info->l2h_th_ini - EDCCA_ADC_BACKOFF)
4583 l2h = dm_info->l2h_th_ini;
4584 h2l = l2h - EDCCA_L2H_H2L_DIFF;
4594 const struct rtw_chip_info *chip = rtwdev->chip;
4597 words = (pkt_info->pkt_offset * 8 + chip->tx_pkt_desc_sz) / 2;
5036 /* Shared-Antenna Coex Table */
5038 {0xffffffff, 0xffffffff}, /* case-0 */
5043 {0xfafafafa, 0xfafafafa}, /* case-5 */
5048 {0x66555555, 0x6a5a5a5a}, /* case-10 */
5053 {0x66555555, 0xaaaaaaaa}, /* case-15 */
5058 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
5063 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
5068 {0x66556aaa, 0x6a5a6aaa}, /*case-30*/
5075 /* Non-Shared-Antenna Coex Table */
5077 {0xffffffff, 0xffffffff}, /* case-100 */
5082 {0xfafafafa, 0xfafafafa}, /* case-105 */
5087 {0x66555555, 0x6a5a5a5a}, /* case-110 */
5092 {0xffff55ff, 0xffff55ff}, /* case-115 */
5097 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
5103 /* Shared-Antenna TDMA */
5105 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
5106 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
5110 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
5115 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
5120 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
5125 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
5130 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
5135 /* Non-Shared-Antenna TDMA */
5137 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
5142 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
5147 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
5152 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
5157 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
5161 /* rssi in percentage % (dbm = % - 100) */
5169 {0, 16, false, 7}, /* for WL-CPT */
5179 {0, 16, false, 7}, /* for WL-CPT */
5429 .max_scan_ie_len = (RTW_PROBE_PG_CNT - 1) * TX_PAGE_SIZE,