Lines Matching defs:rtwdev
48 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
50 struct rtw_hal *hal = &rtwdev->hal;
51 struct rtw_efuse *efuse = &rtwdev->efuse;
90 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4)
93 switch (rtw_hci_type(rtwdev)) {
118 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev)
123 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000);
133 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev)
135 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
136 u8 swing_idx = rtw8821c_get_swing_index(rtwdev);
148 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
151 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev)
153 rtw_bf_phy_init(rtwdev);
155 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);
158 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
160 struct rtw_hal *hal = &rtwdev->hal;
164 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
166 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
170 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
172 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
174 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
176 rtw_write8(rtwdev, REG_RF_CTRL,
179 rtw_write8(rtwdev, REG_WLRF1 + 3,
184 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
186 rtw_phy_load_tables(rtwdev);
188 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
189 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
190 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);
194 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
195 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
196 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
197 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
199 rtw_phy_init(rtwdev);
200 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
202 rtw8821c_pwrtrack_init(rtwdev);
204 rtw8821c_phy_bf_init(rtwdev);
207 static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
213 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
214 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
216 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
217 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
221 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
222 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
224 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
225 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
226 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
227 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
228 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5));
231 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
232 rtw_write16(rtwdev, REG_TXPAUSE, 0);
233 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
234 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
235 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
236 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
237 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
238 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
239 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
242 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
245 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
246 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
247 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
248 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
251 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
252 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
253 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
254 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
255 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
256 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
257 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40);
258 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1));
259 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL,
261 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
262 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
267 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
271 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
273 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
276 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set)
280 rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST);
281 rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN);
283 reg = rtw_read32(rtwdev, REG_RFECTL);
289 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA);
290 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA);
295 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA);
296 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA);
307 rtw_write32(rtwdev, REG_RFECTL, reg);
310 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
312 struct rtw_hal *hal = &rtwdev->hal;
315 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
345 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG);
347 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG);
348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);
349 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf);
351 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA);
352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);
355 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
358 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
361 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
367 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
368 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
371 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
372 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
373 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
374 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);
377 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
378 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
379 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
380 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
384 static void rtw8821c_cck_tx_filter_srrc(struct rtw_dev *rtwdev, u8 channel, u8 bw)
386 struct rtw_hal *hal = &rtwdev->hal;
389 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c);
390 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
391 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
392 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
394 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
395 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
396 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
397 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
398 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
399 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
400 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
401 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
402 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
403 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
406 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xf8fe);
407 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x64b80c1c);
408 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x8810);
409 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x01235667);
411 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
412 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
413 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027);
414 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
415 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027);
416 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
417 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00029);
418 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
419 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00026);
420 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
422 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c);
423 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
425 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
427 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
430 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
431 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
432 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
433 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
434 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
435 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
436 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
437 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
438 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
439 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
443 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
446 struct rtw_hal *hal = &rtwdev->hal;
450 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
451 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
452 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
453 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
455 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0);
456 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
458 if (rtw_regd_srrc(rtwdev)) {
459 rtw8821c_cck_tx_filter_srrc(rtwdev, channel, bw);
465 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
466 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
467 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
469 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
471 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
473 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
477 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
478 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
479 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
480 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
483 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1);
485 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2);
487 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3);
490 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
492 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
494 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
496 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
503 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
506 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
508 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
512 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
514 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
516 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
520 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
522 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
525 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
529 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
531 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
534 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
537 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
539 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
540 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
543 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
546 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
548 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
549 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
554 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel)
556 struct rtw_efuse efuse = rtwdev->efuse;
568 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
571 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
572 rtw8821c_get_bb_swing(rtwdev, channel));
573 rtw8821c_pwrtrack_init(rtwdev);
576 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
579 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
580 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx);
581 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
582 rtw8821c_set_channel_rf(rtwdev, channel, bw);
583 rtw8821c_set_channel_rxdfir(rtwdev, bw);
586 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx)
588 struct rtw_efuse *efuse = &rtwdev->efuse;
603 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx);
613 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
616 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
624 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx);
633 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
636 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
662 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
671 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
674 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
677 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
682 static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
687 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
717 query_phy_status(rtwdev, phy_status, pkt_stat);
720 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
724 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
726 struct rtw_hal *hal = &rtwdev->hal;
739 rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
746 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev)
748 struct rtw_hal *hal = &rtwdev->hal;
756 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs);
761 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev)
763 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
770 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
771 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
772 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
780 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
784 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
788 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
792 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
796 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
800 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
805 rtw_write32_set(rtwdev, REG_FAS, BIT(17));
806 rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
807 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15));
808 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15));
809 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
810 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
813 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev)
821 if (rtw_is_assoc(rtwdev))
824 rtw_fw_do_iqk(rtwdev, ¶);
827 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
832 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
834 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
835 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
836 rtw_dbg(rtwdev, RTW_DBG_PHY,
841 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev)
843 rtw8821c_do_iqk(rtwdev);
847 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev)
850 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
853 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
856 rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE);
859 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
860 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
863 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
865 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
867 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
870 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE,
874 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
877 struct rtw_coex *coex = &rtwdev->coex;
907 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
908 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
910 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
925 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
929 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
930 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
932 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
936 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
940 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
941 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
942 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
946 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
949 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA,
953 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
954 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
957 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
958 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
963 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
964 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
966 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
967 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
971 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
974 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
976 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN);
977 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN);
978 rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN);
979 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS);
980 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT);
981 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT);
984 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
986 struct rtw_coex *coex = &rtwdev->coex;
988 struct rtw_efuse *efuse = &rtwdev->efuse;
1026 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1028 struct rtw_coex *coex = &rtwdev->coex;
1030 struct rtw_efuse *efuse = &rtwdev->efuse;
1042 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1046 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
1050 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1088 rtw_warn(rtwdev, "swing index overflow\n");
1096 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
1102 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower,
1104 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx);
1105 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
1109 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev)
1111 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1114 u8 channel = rtwdev->hal.current_channel;
1115 u8 band_width = rtwdev->hal.current_band_width;
1116 u8 regd = rtw_regd_get(rtwdev);
1118 u8 max_pwr_idx = rtwdev->chip->max_power_index;
1120 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate,
1128 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower);
1131 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev)
1133 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1137 rtw_phy_config_swing_table(rtwdev, &swing_table);
1139 if (rtwdev->efuse.thermal_meter[0] == 0xff)
1142 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1144 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1148 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1152 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1157 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A,
1165 rtw8821c_pwrtrack_set(rtwdev);
1168 if (rtw_phy_pwrtrack_need_iqk(rtwdev))
1169 rtw8821c_do_iqk(rtwdev);
1172 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev)
1174 struct rtw_efuse *efuse = &rtwdev->efuse;
1175 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1181 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1187 rtw8821c_phy_pwrtrack(rtwdev);
1191 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev,
1196 rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
1198 rtw_bf_remove_bfee_su(rtwdev, bfee);
1201 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
1206 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
1208 rtw_bf_remove_bfee_mu(rtwdev, bfee);
1211 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
1215 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
1217 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
1219 rtw_warn(rtwdev, "wrong bfee role\n");
1222 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1224 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1228 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1234 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) &&
1235 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1;
1236 rtw_dbg(rtwdev, RTW_DBG_PHY,
1238 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx,
1245 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1246 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1250 static void rtw8821c_fill_txdesc_checksum(struct rtw_dev *rtwdev,