Lines Matching defs:rtwdev
12 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw,
26 rtw_write8(rtwdev, REG_DATA_SC,
29 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL);
42 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32);
44 if (rtw_chip_wcpu_11n(rtwdev))
47 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL);
49 rtw_write32(rtwdev, REG_AFE_CTRL1, value32);
51 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
52 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
54 value8 = rtw_read8(rtwdev, REG_CCK_CHECK);
58 rtw_write8(rtwdev, REG_CCK_CHECK, value8);
62 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev)
68 rtw_write8(rtwdev, REG_RSV_CTRL, 0);
70 if (rtw_chip_wcpu_11n(rtwdev)) {
71 if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO)
72 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL);
74 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL);
78 switch (rtw_hci_type(rtwdev)) {
80 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS);
83 rtw_write8_clr(rtwdev, REG_SDIO_HSUS_CTRL, BIT_HCI_SUS_REQ);
86 if (rtw_read8(rtwdev, REG_SDIO_HSUS_CTRL) & BIT_HCI_RESUME_RDY)
93 rtw_err(rtwdev, "failed to poll REG_SDIO_HSUS_CTRL[1]");
97 if (rtw_sdio_is_sdio30_supported(rtwdev))
98 rtw_write8_set(rtwdev, REG_HCI_OPT_CTRL + 2,
101 rtw_write8_clr(rtwdev, REG_HCI_OPT_CTRL + 2,
111 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1);
113 rtw_write32(rtwdev, REG_PAD_CTRL1, value32);
115 value32 = rtw_read32(rtwdev, REG_LED_CFG);
117 rtw_write32(rtwdev, REG_LED_CFG, value32);
119 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG);
121 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32);
124 value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
126 rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8);
128 value8 = rtw_read8(rtwdev, REG_RF_CTRL);
130 rtw_write8(rtwdev, REG_RF_CTRL, value8);
132 value32 = rtw_read32(rtwdev, REG_WLRF1);
134 rtw_write32(rtwdev, REG_WLRF1, value32);
139 static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target)
147 rtwdev, addr) == 0;
150 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev,
161 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
164 if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE)
168 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL);
169 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
170 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
171 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
172 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
173 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
174 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
176 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
180 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n",
185 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask,
205 value = rtw_read8(rtwdev, offset);
208 rtw_write8(rtwdev, offset, value);
211 if (rtw_pwr_cmd_polling(rtwdev, cur_cmd))
230 static int rtw_pwr_seq_parser(struct rtw_dev *rtwdev,
240 cut = rtwdev->hal.cut_version;
242 switch (rtw_hci_type(rtwdev)) {
261 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd);
271 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on)
273 const struct rtw_chip_info *chip = rtwdev->chip;
280 if (rtw_chip_wcpu_11ac(rtwdev)) {
281 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr);
284 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) {
286 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm);
290 if (rtw_read8(rtwdev, REG_CR) == 0xea)
292 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
293 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0)))
301 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) {
302 imr = rtw_read32(rtwdev, REG_SDIO_HIMR);
303 rtw_write32(rtwdev, REG_SDIO_HIMR, 0);
307 clear_bit(RTW_FLAG_POWERON, rtwdev->flags);
310 ret = rtw_pwr_seq_parser(rtwdev, pwr_seq);
312 if (pwr_on && rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) {
316 rtw_write8_clr(rtwdev, REG_SYS_STATUS1 + 1, BIT(0));
319 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
320 rtw_write32(rtwdev, REG_SDIO_HIMR, imr);
323 set_bit(RTW_FLAG_POWERON, rtwdev->flags);
328 static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
330 u8 sys_func_en = rtwdev->chip->sys_func_en;
334 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON);
336 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value);
338 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en);
339 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C;
340 rtw_write8(rtwdev, REG_CR_EXT + 3, value8);
343 tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL);
345 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
346 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
347 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value);
353 static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev)
355 rtw_write8(rtwdev, REG_CR, 0xff);
357 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f);
360 rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN);
361 rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC);
363 rtw_write16(rtwdev, REG_CR, 0x2ff);
368 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
370 if (rtw_chip_wcpu_11n(rtwdev))
371 return __rtw_mac_init_system_cfg_legacy(rtwdev);
373 return __rtw_mac_init_system_cfg(rtwdev);
376 int rtw_mac_power_on(struct rtw_dev *rtwdev)
380 ret = rtw_mac_pre_system_cfg(rtwdev);
384 ret = rtw_mac_power_switch(rtwdev, true);
386 rtw_mac_power_switch(rtwdev, false);
388 ret = rtw_mac_pre_system_cfg(rtwdev);
392 ret = rtw_mac_power_switch(rtwdev, true);
399 ret = rtw_mac_init_system_cfg(rtwdev);
406 rtw_err(rtwdev, "mac power on failed");
410 void rtw_mac_power_off(struct rtw_dev *rtwdev)
412 rtw_mac_power_switch(rtwdev, false);
438 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable)
442 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
445 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
448 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
451 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
457 static void download_firmware_reg_backup(struct rtw_dev *rtwdev,
466 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1);
469 rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp);
474 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR);
481 rtw_write8(rtwdev, REG_CR, tmp);
482 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
487 bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1);
491 bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN;
493 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200);
494 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val);
496 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
497 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG);
500 tmp = rtw_read8(rtwdev, REG_BCN_CTRL);
506 rtw_write8(rtwdev, REG_BCN_CTRL, tmp);
511 static void download_firmware_reset_platform(struct rtw_dev *rtwdev)
513 rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
514 rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
515 rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
516 rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
519 static void download_firmware_reg_restore(struct rtw_dev *rtwdev,
523 rtw_restore_reg(rtwdev, bckp, bckp_num);
528 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
538 ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size);
544 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size)
548 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
552 ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size);
554 rtw_err(rtwdev, "failed to download rsvd page\n");
560 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl)
562 rtw_write32(rtwdev, REG_DDMA_CH0SA, src);
563 rtw_write32(rtwdev, REG_DDMA_CH0DA, dst);
564 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl);
566 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
572 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst,
577 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
584 if (iddma_enable(rtwdev, src, dst, ch0_ctrl))
590 int rtw_ddma_to_fw_fifo(struct rtw_dev *rtwdev, u32 ocp_src, u32 size)
594 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) {
595 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to start ddma\n");
601 if (iddma_enable(rtwdev, ocp_src, OCPBASE_RXBUF_FW_88XX, ch0_ctrl)) {
602 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to complete ddma\n");
610 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr)
614 fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL);
616 if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {
620 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
624 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
627 rtw_err(rtwdev, "invalid fw checksum\n");
634 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
637 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
644 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data,
647 const struct rtw_chip_info *chip = rtwdev->chip;
661 val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL);
663 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val);
671 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7),
676 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX +
688 if (!check_fw_checksum(rtwdev, dst))
695 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size)
714 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800);
716 rtw_write16(rtwdev, REG_MCUFW_CTRL, val);
721 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size);
728 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size);
736 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr,
745 static int download_firmware_validate(struct rtw_dev *rtwdev)
749 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) {
750 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK;
752 rtw_err(rtwdev, "invalid fw key\n");
759 static void download_firmware_end_flow(struct rtw_dev *rtwdev)
763 rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF);
766 fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL);
771 rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
774 static int __rtw_download_firmware(struct rtw_dev *rtwdev,
786 if (!ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp))
789 wlan_cpu_enable(rtwdev, false);
791 download_firmware_reg_backup(rtwdev, bckp);
792 download_firmware_reset_platform(rtwdev);
794 ret = start_download_firmware(rtwdev, data, size);
798 download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM);
800 download_firmware_end_flow(rtwdev);
802 wlan_cpu_enable(rtwdev, true);
804 if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) {
809 ret = download_firmware_validate(rtwdev);
814 rtw_hci_setup(rtwdev);
816 rtwdev->h2c.last_box_num = 0;
817 rtwdev->h2c.seq = 0;
819 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
825 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
826 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
831 static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en)
836 wlan_cpu_enable(rtwdev, false);
837 wlan_cpu_enable(rtwdev, true);
839 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
842 if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN)
844 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
847 rtw_err(rtwdev, "failed to check fw download ready\n");
849 rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN);
851 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
856 write_firmware_page(struct rtw_dev *rtwdev, u32 page, const u8 *data, u32 size)
869 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
872 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
875 rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr));
883 rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data));
888 download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size)
900 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT);
903 write_firmware_page(rtwdev, page, data, DLFW_PAGE_SIZE_LEGACY);
907 write_firmware_page(rtwdev, page, data, last_page_size);
909 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) {
910 rtw_err(rtwdev, "failed to check download firmware report\n");
917 static int download_firmware_validate_legacy(struct rtw_dev *rtwdev)
922 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
925 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
927 wlan_cpu_enable(rtwdev, false);
928 wlan_cpu_enable(rtwdev, true);
931 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
937 rtw_err(rtwdev, "failed to validate firmware\n");
941 static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev,
947 if (rtwdev->chip->id == RTW_CHIP_TYPE_8703B &&
948 rtw_read8_mask(rtwdev, REG_MCUFW_CTRL, BIT_RAM_DL_SEL)) {
949 rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00);
952 en_download_firmware_legacy(rtwdev, true);
953 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size);
954 en_download_firmware_legacy(rtwdev, false);
958 ret = download_firmware_validate_legacy(rtwdev);
963 rtw_hci_setup(rtwdev);
965 rtwdev->h2c.last_box_num = 0;
966 rtwdev->h2c.seq = 0;
968 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
975 int _rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw)
977 if (rtw_chip_wcpu_11n(rtwdev))
978 return __rtw_download_firmware_legacy(rtwdev, fw);
980 return __rtw_download_firmware(rtwdev, fw);
983 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw)
987 ret = _rtw_download_firmware(rtwdev, fw);
991 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE &&
992 rtwdev->chip->id == RTW_CHIP_TYPE_8821C)
993 rtw_fw_set_recover_bt_device(rtwdev);
998 static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues)
1000 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn;
1015 static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev,
1018 const struct rtw_chip_info *chip = rtwdev->chip;
1032 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) :
1033 rtw_read8(rtwdev, addr->rsvd);
1034 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) :
1035 rtw_read8(rtwdev, addr->avail);
1049 rtw_dbg(rtwdev, RTW_DBG_UNEXP,
1053 static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev,
1060 __rtw_mac_flush_prio_queue(rtwdev, q, drop);
1063 void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop)
1071 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn)
1074 prio_queues = get_priority_queues(rtwdev, queues);
1076 rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop);
1079 static int txdma_queue_mapping(struct rtw_dev *rtwdev)
1081 const struct rtw_chip_info *chip = rtwdev->chip;
1085 switch (rtw_hci_type(rtwdev)) {
1090 if (rtwdev->hci.bulkout_num == 2)
1092 else if (rtwdev->hci.bulkout_num == 3)
1094 else if (rtwdev->hci.bulkout_num == 4)
1106 rtwdev->fifo.rqpn = rqpn;
1113 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map);
1115 rtw_write8(rtwdev, REG_CR, 0);
1116 rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE);
1117 if (rtw_chip_wcpu_11ac(rtwdev))
1118 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
1120 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) {
1121 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG);
1122 rtw_write32(rtwdev, REG_SDIO_TX_CTRL, 0);
1123 } else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) {
1124 rtw_write8_set(rtwdev, REG_TXDMA_PQ_MAP, BIT_RXDMA_ARBBW_EN);
1130 static int set_trx_fifo_info(struct rtw_dev *rtwdev)
1132 const struct rtw_chip_info *chip = rtwdev->chip;
1133 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1140 if (rtw_chip_wcpu_11n(rtwdev))
1158 if (rtw_chip_wcpu_11ac(rtwdev)) {
1176 rtw_err(rtwdev, "wrong rsvd driver address\n");
1183 static int __priority_queue_cfg(struct rtw_dev *rtwdev,
1187 const struct rtw_chip_info *chip = rtwdev->chip;
1188 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1190 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num);
1191 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num);
1192 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num);
1193 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num);
1194 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num);
1195 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN);
1197 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary);
1198 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16);
1200 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary);
1201 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
1202 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
1203 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
1205 if (rtwdev->hci.type == RTW_HCI_TYPE_USB) {
1206 rtw_write8_mask(rtwdev, REG_AUTO_LLT_V1, BIT_MASK_BLK_DESC_NUM,
1209 rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3, chip->usb_tx_agg_desc_num);
1210 rtw_write8_set(rtwdev, REG_TXDMA_OFFSET_CHK + 1, BIT(1));
1213 rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
1215 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))
1218 rtw_write8(rtwdev, REG_CR + 3, 0);
1223 static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev,
1227 const struct rtw_chip_info *chip = rtwdev->chip;
1228 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1232 rtw_write32(rtwdev, REG_RQPN_NPQ, val32);
1234 rtw_write32(rtwdev, REG_RQPN, val32);
1236 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
1237 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1);
1238 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
1239 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
1240 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
1241 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
1243 rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT);
1245 if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0))
1251 static int priority_queue_cfg(struct rtw_dev *rtwdev)
1253 const struct rtw_chip_info *chip = rtwdev->chip;
1254 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1259 ret = set_trx_fifo_info(rtwdev);
1263 switch (rtw_hci_type(rtwdev)) {
1268 if (rtwdev->hci.bulkout_num == 2)
1270 else if (rtwdev->hci.bulkout_num == 3)
1272 else if (rtwdev->hci.bulkout_num == 4)
1286 if (rtw_chip_wcpu_11n(rtwdev))
1287 return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num);
1289 return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num);
1292 static int init_h2c(struct rtw_dev *rtwdev)
1294 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1302 if (rtw_chip_wcpu_11n(rtwdev))
1308 value32 = rtw_read32(rtwdev, REG_H2C_HEAD);
1310 rtw_write32(rtwdev, REG_H2C_HEAD, value32);
1312 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR);
1314 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32);
1316 value32 = rtw_read32(rtwdev, REG_H2C_TAIL);
1319 rtw_write32(rtwdev, REG_H2C_TAIL, value32);
1321 value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1323 rtw_write8(rtwdev, REG_H2C_INFO, value8);
1325 value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1327 rtw_write8(rtwdev, REG_H2C_INFO, value8);
1329 value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1);
1331 rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8);
1333 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF;
1334 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF;
1338 rtw_err(rtwdev, "H2C queue mismatch\n");
1345 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev)
1349 ret = txdma_queue_mapping(rtwdev);
1353 ret = priority_queue_cfg(rtwdev);
1357 ret = init_h2c(rtwdev);
1364 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev)
1368 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE);
1369 if (rtw_chip_wcpu_11ac(rtwdev)) {
1370 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1);
1374 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8);
1376 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS);
1377 rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9));
1382 int rtw_mac_init(struct rtw_dev *rtwdev)
1384 const struct rtw_chip_info *chip = rtwdev->chip;
1387 ret = rtw_init_trx_cfg(rtwdev);
1391 ret = chip->ops->mac_init(rtwdev);
1395 ret = rtw_drv_info_cfg(rtwdev);
1399 rtw_hci_interface_cfg(rtwdev);