Lines Matching +full:chip +full:- +full:to +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
16 const struct rtw_chip_info *chip = rtwdev->chip;
17 u8 tol = chip->rssi_tolerance;
39 const struct rtw_chip_info *chip = rtwdev->chip;
40 struct rtw_coex *coex = &rtwdev->coex;
41 struct rtw_coex_stat *coex_stat = &coex->stat;
44 if (!chip->scbd_support)
48 if (coex_stat->wl_tx_limit_en == tx_limit_en &&
49 coex_stat->wl_ampdu_limit_en == ampdu_limit_en)
52 if (!coex_stat->wl_tx_limit_en) {
53 coex_stat->darfrc = rtw_read32(rtwdev, REG_DARFRC);
54 coex_stat->darfrch = rtw_read32(rtwdev, REG_DARFRCH);
55 coex_stat->retry_limit = rtw_read16(rtwdev, REG_RETRY_LIMIT);
58 if (!coex_stat->wl_ampdu_limit_en)
59 coex_stat->ampdu_max_time =
62 coex_stat->wl_tx_limit_en = tx_limit_en;
63 coex_stat->wl_ampdu_limit_en = ampdu_limit_en;
71 /* set queue life time to avoid can't reach tx retry limit
85 rtw_write16(rtwdev, REG_RETRY_LIMIT, coex_stat->retry_limit);
86 rtw_write32(rtwdev, REG_DARFRC, coex_stat->darfrc);
87 rtw_write32(rtwdev, REG_DARFRCH, coex_stat->darfrch);
94 coex_stat->ampdu_max_time);
99 struct rtw_coex *coex = &rtwdev->coex;
100 struct rtw_coex_dm *coex_dm = &coex->dm;
104 if (!coex->under_5g && coex_dm->bt_status != COEX_BTSTATUS_NCON_IDLE) {
114 struct rtw_coex *coex = &rtwdev->coex;
115 struct rtw_coex_dm *coex_dm = &coex->dm;
116 struct rtw_coex_stat *coex_stat = &coex->stat;
117 struct rtw_efuse *efuse = &rtwdev->efuse;
121 if (coex_stat->bt_disabled)
124 if (efuse->share_ant || ant_distance <= 5 || !coex_stat->wl_gl_busy)
127 if (ant_distance >= 40 || coex_stat->bt_hid_pair_num >= 2)
131 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[1]) &&
132 COEX_RSSI_HIGH(coex_dm->bt_rssi_state[0]))
135 if (coex_stat->wl_tput_dir == COEX_WL_TPUT_TX)
136 bt_rssi = coex_dm->bt_rssi_state[0];
138 bt_rssi = coex_dm->bt_rssi_state[1];
140 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[3]) &&
142 coex_stat->cnt_wl[COEX_CNT_WL_SCANAP] <= 5)
150 struct rtw_coex *coex = &rtwdev->coex;
151 struct rtw_coex_stat *coex_stat = &coex->stat;
160 coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] = 0;
162 coex_stat->wl_slot_extend = enable;
168 struct rtw_coex *coex = &rtwdev->coex;
169 struct rtw_coex_stat *coex_stat = &coex->stat;
171 if (coex->manual_control || coex->stop_dm)
175 if (coex_stat->tdma_timer_base == 3 && coex_stat->wl_slot_extend) {
177 "[BTCoex], set h2c 0x69 opcode 12 to turn off 5ms WL slot extend!!\n");
182 if (coex_stat->wl_slot_extend && coex_stat->wl_force_lps_ctrl &&
183 !coex_stat->wl_cck_lock_ever) {
184 if (coex_stat->wl_fw_dbg_info[7] <= 5)
185 coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND]++;
187 coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] = 0;
191 coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND]);
193 if (coex_stat->cnt_wl[COEX_CNT_WL_5MS_NOEXTEND] == 7) {
195 "[BTCoex], set h2c 0x69 opcode 12 to turn off 5ms WL slot extend!!\n");
198 } else if (!coex_stat->wl_slot_extend && coex_stat->wl_cck_lock) {
200 "[BTCoex], set h2c 0x69 opcode 12 to turn on 5ms WL slot extend!!\n");
208 struct rtw_coex *coex = &rtwdev->coex;
209 struct rtw_coex_stat *coex_stat = &coex->stat;
210 struct rtw_coex_dm *coex_dm = &coex->dm;
214 if (coex_stat->wl_coex_mode != COEX_WLINK_2G1PORT &&
215 coex_stat->wl_coex_mode != COEX_WLINK_2GFREE)
218 if (coex_dm->bt_status == COEX_BTSTATUS_INQ_PAGE ||
219 coex_stat->bt_setup_link) {
220 coex_stat->wl_cck_lock = false;
221 coex_stat->wl_cck_lock_pre = false;
225 if (coex_stat->wl_rx_rate <= COEX_CCK_2 ||
226 coex_stat->wl_rts_rx_rate <= COEX_CCK_2)
229 if (coex_stat->wl_connected && coex_stat->wl_gl_busy &&
230 COEX_RSSI_HIGH(coex_dm->wl_rssi_state[3]) &&
231 (coex_dm->bt_status == COEX_BTSTATUS_ACL_BUSY ||
232 coex_dm->bt_status == COEX_BTSTATUS_ACL_SCO_BUSY ||
233 coex_dm->bt_status == COEX_BTSTATUS_SCO_BUSY)) {
235 coex_stat->wl_cck_lock = true;
241 coex_stat->wl_cck_lock = false;
247 coex_stat->wl_cck_lock = false;
251 if (coex_stat->wl_cck_lock && !coex_stat->wl_cck_lock_pre)
252 ieee80211_queue_delayed_work(rtwdev->hw, &coex->wl_ccklock_work,
255 coex_stat->wl_cck_lock_pre = coex_stat->wl_cck_lock;
260 struct rtw_coex *coex = &rtwdev->coex;
261 struct rtw_coex_stat *coex_stat = &coex->stat;
262 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
267 cnt_cck = dm_info->cck_ok_cnt + dm_info->cck_err_cnt;
269 if (!coex_stat->wl_gl_busy && !wl_cck_lock) {
271 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] < 5)
272 coex_stat->cnt_wl[COEX_CNT_WL_NOISY2]++;
274 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] == 5) {
275 coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] = 0;
276 coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] = 0;
279 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] < 5)
280 coex_stat->cnt_wl[COEX_CNT_WL_NOISY0]++;
282 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] == 5) {
283 coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] = 0;
284 coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] = 0;
287 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] < 5)
288 coex_stat->cnt_wl[COEX_CNT_WL_NOISY1]++;
290 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] == 5) {
291 coex_stat->cnt_wl[COEX_CNT_WL_NOISY0] = 0;
292 coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] = 0;
296 if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY2] == 5)
297 coex_stat->wl_noisy_level = 2;
298 else if (coex_stat->cnt_wl[COEX_CNT_WL_NOISY1] == 5)
299 coex_stat->wl_noisy_level = 1;
301 coex_stat->wl_noisy_level = 0;
304 coex_stat->wl_noisy_level);
310 struct rtw_coex *coex = &rtwdev->coex;
311 struct rtw_coex_stat *coex_stat = &coex->stat;
314 u16 tbtt_interval = coex_stat->wl_beacon_interval;
316 if (coex_stat->tdma_timer_base == type)
319 coex_stat->tdma_timer_base = type;
327 para[1] = PARA1_H2C69_TDMA_4SLOT; /* 4-slot */
337 times--;
350 /* no 5ms_wl_slot_extend for 4-slot mode */
351 if (coex_stat->tdma_timer_base == 3)
368 const struct rtw_chip_info *chip = rtwdev->chip;
369 struct rtw_coex *coex = &rtwdev->coex;
370 struct rtw_coex_stat *coex_stat = &coex->stat;
373 if (!chip->scbd_support)
376 val |= coex_stat->score_board;
381 if (!chip->new_scbd10_def && (bitpos & COEX_SCBD_FIX2M)) {
393 if (val != coex_stat->score_board) {
394 coex_stat->score_board = val;
403 const struct rtw_chip_info *chip = rtwdev->chip;
405 if (!chip->scbd_support)
413 const struct rtw_chip_info *chip = rtwdev->chip;
414 struct rtw_coex *coex = &rtwdev->coex;
415 struct rtw_coex_stat *coex_stat = &coex->stat;
416 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
421 if (coex_rfe->wlg_at_btg && chip->scbd_support &&
422 coex_stat->bt_iqk_state != 0xff) {
445 coex_stat->bt_iqk_state = 0xff;
451 struct rtw_coex *coex = &rtwdev->coex;
452 struct rtw_coex_stat *coex_stat = &coex->stat;
454 if (coex_stat->bt_disabled)
469 struct rtw_coex *coex = &rtwdev->coex;
470 struct rtw_coex_stat *coex_stat = &coex->stat;
474 coex_stat->hi_pri_tx = FIELD_GET(MASKLWORD, tmp);
475 coex_stat->hi_pri_rx = FIELD_GET(MASKHWORD, tmp);
478 coex_stat->lo_pri_tx = FIELD_GET(MASKLWORD, tmp);
479 coex_stat->lo_pri_rx = FIELD_GET(MASKHWORD, tmp);
485 "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n",
486 coex_stat->hi_pri_rx, coex_stat->hi_pri_tx,
487 coex_stat->lo_pri_rx, coex_stat->lo_pri_tx);
492 const struct rtw_chip_info *chip = rtwdev->chip;
493 struct rtw_coex *coex = &rtwdev->coex;
494 struct rtw_coex_stat *coex_stat = &coex->stat;
495 struct rtw_coex_dm *coex_dm = &coex->dm;
499 if (chip->scbd_support) {
504 if (coex_stat->bt_disabled != bt_disabled) {
506 "[BTCoex], BT state changed (%d) -> (%d)\n",
507 coex_stat->bt_disabled, bt_disabled);
509 coex_stat->bt_disabled = bt_disabled;
510 coex_stat->bt_ble_scan_type = 0;
511 coex_dm->cur_bt_lna_lvl = 0;
513 if (!coex_stat->bt_disabled) {
514 coex_stat->bt_reenable = true;
515 ieee80211_queue_delayed_work(rtwdev->hw,
516 &coex->bt_reenable_work,
519 coex_stat->bt_mailbox_reply = false;
520 coex_stat->bt_reenable = false;
527 const struct rtw_chip_info *chip = rtwdev->chip;
528 struct rtw_coex *coex = &rtwdev->coex;
529 struct rtw_coex_stat *coex_stat = &coex->stat;
530 struct rtw_coex_dm *coex_dm = &coex->dm;
531 struct rtw_traffic_stats *stats = &rtwdev->stats;
540 scan = test_bit(RTW_FLAG_SCANNING, rtwdev->flags);
541 coex_stat->wl_connected = !!rtwdev->sta_cnt;
543 wl_busy = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
544 if (wl_busy != coex_stat->wl_gl_busy) {
546 coex_stat->wl_gl_busy = true;
548 ieee80211_queue_delayed_work(rtwdev->hw,
549 &coex->wl_remain_work,
553 if (stats->tx_throughput > stats->rx_throughput)
554 coex_stat->wl_tput_dir = COEX_WL_TPUT_TX;
556 coex_stat->wl_tput_dir = COEX_WL_TPUT_RX;
560 coex_stat->wl_linkscan_proc = true;
562 coex_stat->wl_linkscan_proc = false;
567 rssi_state = coex_dm->wl_rssi_state[i];
568 rssi_step = chip->wl_rssi_step[i];
569 rssi = rtwdev->dm_info.min_rssi;
572 coex_dm->wl_rssi_state[i] = rssi_state;
575 if (coex_stat->wl_linkscan_proc || coex_stat->wl_hi_pri_task1 ||
576 coex_stat->wl_hi_pri_task2 || coex_stat->wl_gl_busy)
595 if (rtwdev->hal.current_band_type == RTW_BAND_5G)
602 coex->under_5g = is_5G;
610 pkt_offset = *((u32 *)resp->cb);
611 c2h = (struct rtw_c2h_cmd *)(resp->data + pkt_offset);
613 return c2h->payload;
618 struct rtw_coex *coex = &rtwdev->coex;
626 skb_queue_tail(&coex->queue, skb);
627 wake_up(&coex->wait);
633 struct rtw_coex *coex = &rtwdev->coex;
636 lockdep_assert_held(&rtwdev->mutex);
640 if (!wait_event_timeout(coex->wait, !skb_queue_empty(&coex->queue),
646 skb_resp = skb_dequeue(&coex->queue);
648 rtw_err(rtwdev, "failed to get coex info response\n");
708 const struct rtw_chip_info *chip = rtwdev->chip;
709 struct rtw_coex *coex = &rtwdev->coex;
710 struct rtw_coex_stat *coex_stat = &coex->stat;
711 struct rtw_coex_dm *coex_dm = &coex->dm;
719 rssi_state = coex_dm->bt_rssi_state[i];
720 rssi_step = chip->bt_rssi_step[i];
721 rssi = coex_stat->bt_rssi;
724 coex_dm->bt_rssi_state[i] = rssi_state;
727 if (coex_stat->bt_ble_scan_en &&
728 coex_stat->cnt_bt[COEX_CNT_BT_INFOUPDATE] % 3 == 0) {
732 coex_stat->bt_ble_scan_type = scan_type;
733 if ((coex_stat->bt_ble_scan_type & 0x1) == 0x1)
734 coex_stat->bt_init_scan = true;
736 coex_stat->bt_init_scan = false;
740 coex_stat->bt_profile_num = 0;
743 if (!(coex_stat->bt_info_lb2 & COEX_INFO_CONNECTION)) {
744 coex_stat->bt_link_exist = false;
745 coex_stat->bt_pan_exist = false;
746 coex_stat->bt_a2dp_exist = false;
747 coex_stat->bt_hid_exist = false;
748 coex_stat->bt_hfp_exist = false;
751 coex_stat->bt_link_exist = true;
752 if (coex_stat->bt_info_lb2 & COEX_INFO_FTP) {
753 coex_stat->bt_pan_exist = true;
754 coex_stat->bt_profile_num++;
756 coex_stat->bt_pan_exist = false;
759 if (coex_stat->bt_info_lb2 & COEX_INFO_A2DP) {
760 coex_stat->bt_a2dp_exist = true;
761 coex_stat->bt_profile_num++;
763 coex_stat->bt_a2dp_exist = false;
766 if (coex_stat->bt_info_lb2 & COEX_INFO_HID) {
767 coex_stat->bt_hid_exist = true;
768 coex_stat->bt_profile_num++;
770 coex_stat->bt_hid_exist = false;
773 if (coex_stat->bt_info_lb2 & COEX_INFO_SCO_ESCO) {
774 coex_stat->bt_hfp_exist = true;
775 coex_stat->bt_profile_num++;
777 coex_stat->bt_hfp_exist = false;
781 if (coex_stat->bt_info_lb2 & COEX_INFO_INQ_PAGE) {
782 coex_dm->bt_status = COEX_BTSTATUS_INQ_PAGE;
783 } else if (!(coex_stat->bt_info_lb2 & COEX_INFO_CONNECTION)) {
784 coex_dm->bt_status = COEX_BTSTATUS_NCON_IDLE;
785 coex_stat->bt_multi_link_remain = false;
786 } else if (coex_stat->bt_info_lb2 == COEX_INFO_CONNECTION) {
787 coex_dm->bt_status = COEX_BTSTATUS_CON_IDLE;
788 } else if ((coex_stat->bt_info_lb2 & COEX_INFO_SCO_ESCO) ||
789 (coex_stat->bt_info_lb2 & COEX_INFO_SCO_BUSY)) {
790 if (coex_stat->bt_info_lb2 & COEX_INFO_ACL_BUSY)
791 coex_dm->bt_status = COEX_BTSTATUS_ACL_SCO_BUSY;
793 coex_dm->bt_status = COEX_BTSTATUS_SCO_BUSY;
794 } else if (coex_stat->bt_info_lb2 & COEX_INFO_ACL_BUSY) {
795 coex_dm->bt_status = COEX_BTSTATUS_ACL_BUSY;
797 coex_dm->bt_status = COEX_BTSTATUS_MAX;
800 coex_stat->cnt_bt[COEX_CNT_BT_INFOUPDATE]++;
803 rtw_coex_get_bt_status_string(coex_dm->bt_status));
808 const struct rtw_chip_info *chip = rtwdev->chip;
809 struct rtw_efuse *efuse = &rtwdev->efuse;
810 struct rtw_coex_dm *coex_dm = &rtwdev->coex.dm;
811 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
817 bw = rtwdev->hal.current_band_width;
820 center_chan = rtwdev->hal.current_channel;
823 (efuse->share_ant && center_chan <= 14 &&
824 coex_stat->wl_coex_mode != COEX_WLINK_2GFREE)) {
832 bw = chip->bt_afh_span_bw40;
834 bw = chip->bt_afh_span_bw20;
835 } else if (chip->afh_5g_num > 1) {
836 for (i = 0; i < chip->afh_5g_num; i++) {
837 if (center_chan == chip->afh_5g[i].wl_5g_ch) {
839 center_chan = chip->afh_5g[i].bt_skip_ch;
840 bw = chip->afh_5g[i].bt_skip_span;
846 coex_dm->wl_ch_info[0] = link;
847 coex_dm->wl_ch_info[1] = center_chan;
848 coex_dm->wl_ch_info[2] = bw;
858 struct rtw_coex *coex = &rtwdev->coex;
859 struct rtw_coex_dm *coex_dm = &coex->dm;
861 if (bt_pwr_dec_lvl == coex_dm->cur_bt_pwr_lvl)
864 coex_dm->cur_bt_pwr_lvl = bt_pwr_dec_lvl;
871 struct rtw_coex *coex = &rtwdev->coex;
872 struct rtw_coex_dm *coex_dm = &coex->dm;
874 if (bt_lna_lvl == coex_dm->cur_bt_lna_lvl)
877 coex_dm->cur_bt_lna_lvl = bt_lna_lvl;
893 struct rtw_coex *coex = &rtwdev->coex;
894 struct rtw_coex_stat *coex_stat = &coex->stat;
897 if (coex->freerun && coex_stat->cnt_wl[COEX_CNT_WL_SCANAP] <= 5)
911 rtw_err(rtwdev, "failed to read indirect register\n");
929 rtw_err(rtwdev, "failed to write indirect register\n");
935 const struct rtw_chip_info *chip = rtwdev->chip;
936 const struct rtw_hw_reg *btg_reg = chip->btg_reg;
942 rtw_write8_set(rtwdev, btg_reg->addr, btg_reg->mask);
947 rtw_write8_clr(rtwdev, btg_reg->addr, btg_reg->mask);
965 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
967 if (!force && state == coex_stat->wl_mimo_ps)
970 coex_stat->wl_mimo_ps = state;
974 rtw_coex_update_wl_ch_info(rtwdev, (u8)coex_stat->wl_connected);
983 const struct rtw_chip_info *chip = rtwdev->chip;
984 struct rtw_efuse *efuse = &rtwdev->efuse;
992 if (efuse->share_ant) {
993 if (table_case < chip->table_sant_num)
994 table_wl = chip->table_sant[table_case].wl;
996 if (table_case < chip->table_nsant_num)
997 table_wl = chip->table_nsant[table_case].wl;
1000 /* tell WL FW WL slot toggle table-A*/
1018 struct rtw_coex *coex = &rtwdev->coex;
1019 struct rtw_coex_stat *coex_stat = &coex->stat;
1030 coex_stat->wl_toggle_interval = interval;
1033 coex_stat->wl_toggle_para[i] = cur_h2c_para[i];
1047 struct rtw_coex *coex = &rtwdev->coex;
1048 struct rtw_coex_dm *coex_dm = &coex->dm;
1051 if (!force && coex_dm->reason != COEX_RSN_LPS) {
1067 const struct rtw_chip_info *chip = rtwdev->chip;
1068 struct rtw_coex *coex = &rtwdev->coex;
1069 struct rtw_coex_dm *coex_dm = &coex->dm;
1070 struct rtw_efuse *efuse = &rtwdev->efuse;
1071 struct rtw_coex_stat *coex_stat = &coex->stat;
1073 coex_dm->cur_table = type;
1075 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Coex_Table - %d\n", type);
1077 if (efuse->share_ant) {
1078 if (type < chip->table_sant_num)
1080 chip->table_sant[type].bt,
1081 chip->table_sant[type].wl);
1083 type = type - 100;
1084 if (type < chip->table_nsant_num)
1086 chip->table_nsant[type].bt,
1087 chip->table_nsant[type].wl);
1089 if (coex_stat->wl_slot_toggle_change)
1095 struct rtw_coex *coex = &rtwdev->coex;
1097 if (coex->manual_control || coex->stop_dm)
1106 struct rtw_coex *coex = &rtwdev->coex;
1107 struct rtw_coex_stat *coex_stat = &coex->stat;
1110 lps_mode = rtwdev->lps_conf.mode;
1114 /* recover to original 32k low power setting */
1115 coex_stat->wl_force_lps_ctrl = false;
1121 coex_stat->wl_force_lps_ctrl = true;
1137 const struct rtw_chip_info *chip = rtwdev->chip;
1138 struct rtw_coex *coex = &rtwdev->coex;
1139 struct rtw_coex_dm *coex_dm = &coex->dm;
1140 struct rtw_coex_stat *coex_stat = &coex->stat;
1157 coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) {
1162 if (chip->pstdma_type == COEX_PSTDMA_FORCE_LPSOFF)
1176 coex_dm->ps_tdma_para[0] = byte1;
1177 coex_dm->ps_tdma_para[1] = byte2;
1178 coex_dm->ps_tdma_para[2] = byte3;
1179 coex_dm->ps_tdma_para[3] = byte4;
1180 coex_dm->ps_tdma_para[4] = byte5;
1185 coex_stat->wl_slot_toggle = true;
1186 coex_stat->wl_slot_toggle_change = false;
1188 coex_stat->wl_slot_toggle_change = coex_stat->wl_slot_toggle;
1189 coex_stat->wl_slot_toggle = false;
1195 const struct rtw_chip_info *chip = rtwdev->chip;
1196 struct rtw_coex *coex = &rtwdev->coex;
1197 struct rtw_coex_dm *coex_dm = &coex->dm;
1198 struct rtw_coex_stat *coex_stat = &coex->stat;
1199 struct rtw_efuse *efuse = &rtwdev->efuse;
1204 if (tcase & TDMA_4SLOT) /* 4-slot (50ms) mode */
1213 if (!force && turn_on == coex_dm->cur_ps_tdma_on &&
1214 type == coex_dm->cur_ps_tdma) {
1217 (coex_dm->cur_ps_tdma_on ? "on" : "off"),
1218 coex_dm->cur_ps_tdma);
1222 wl_busy = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
1224 if ((coex_stat->bt_a2dp_exist &&
1225 (coex_stat->bt_inq_remain || coex_stat->bt_multi_link)) ||
1232 coex_dm->cur_ps_tdma_on = turn_on;
1233 coex_dm->cur_ps_tdma = type;
1235 if (efuse->share_ant) {
1236 if (type < chip->tdma_sant_num)
1238 chip->tdma_sant[type].para[0],
1239 chip->tdma_sant[type].para[1],
1240 chip->tdma_sant[type].para[2],
1241 chip->tdma_sant[type].para[3],
1242 chip->tdma_sant[type].para[4]);
1244 n = type - 100;
1245 if (n < chip->tdma_nsant_num)
1247 chip->tdma_nsant[n].para[0],
1248 chip->tdma_nsant[n].para[1],
1249 chip->tdma_nsant[n].para[2],
1250 chip->tdma_nsant[n].para[3],
1251 chip->tdma_nsant[n].para[4]);
1261 struct rtw_coex *coex = &rtwdev->coex;
1262 struct rtw_coex_stat *coex_stat = &coex->stat;
1263 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1264 struct rtw_coex_dm *coex_dm = &coex->dm;
1268 if (!force && coex_dm->cur_ant_pos_type == phase)
1271 coex_dm->cur_ant_pos_type = phase;
1277 "[BTCoex], coex_stat->bt_disabled = 0x%x\n",
1278 coex_stat->bt_disabled);
1283 "[BTCoex], %s() - PHASE_COEX_POWERON\n", __func__);
1284 /* set path control owner to BT at power-on */
1285 if (coex_stat->bt_disabled)
1295 "[BTCoex], %s() - PHASE_COEX_INIT\n", __func__);
1296 if (coex_stat->bt_disabled) {
1297 /* set GNT_BT to SW low */
1300 /* set GNT_WL to SW high */
1303 /* set GNT_BT to SW high */
1306 /* set GNT_WL to SW low */
1310 /* set path control owner to wl at initial step */
1318 "[BTCoex], %s() - PHASE_WLANONLY_INIT\n", __func__);
1319 /* set GNT_BT to SW Low */
1322 /* set GNT_WL to SW high */
1325 /* set path control owner to wl at initial step */
1333 "[BTCoex], %s() - PHASE_WLAN_OFF\n", __func__);
1334 /* set path control owner to BT */
1342 "[BTCoex], %s() - PHASE_2G_RUNTIME\n", __func__);
1343 /* set GNT_BT to PTA */
1346 /* set GNT_WL to PTA */
1349 /* set path control owner to wl at runtime step */
1357 "[BTCoex], %s() - PHASE_5G_RUNTIME\n", __func__);
1359 /* set GNT_BT to HW PTA */
1362 /* set GNT_WL to SW high */
1365 /* set path control owner to wl at runtime step */
1373 "[BTCoex], %s() - PHASE_2G_FREERUN\n", __func__);
1375 /* set GNT_BT to HW PTA */
1378 /* Set GNT_WL to SW high */
1381 /* set path control owner to wl at runtime step */
1389 "[BTCoex], %s() - PHASE_2G_WLBT\n", __func__);
1390 /* set GNT_BT to HW PTA */
1393 /* Set GNT_WL to HW PTA */
1396 /* set path control owner to wl at runtime step */
1408 coex_rfe->ant_switch_exist)
1461 struct rtw_coex *coex = &rtwdev->coex;
1462 struct rtw_coex_stat *coex_stat = &coex->stat;
1466 if (coex_stat->bt_hfp_exist)
1468 if (coex_stat->bt_hid_exist)
1470 if (coex_stat->bt_a2dp_exist)
1472 if (coex_stat->bt_pan_exist)
1505 if (coex_stat->bt_multi_link) {
1506 if (coex_stat->bt_hid_pair_num > 0)
1528 const struct rtw_chip_info *chip = rtwdev->chip;
1529 struct rtw_efuse *efuse = &rtwdev->efuse;
1533 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1535 if (efuse->share_ant) {
1536 /* Shared-Ant */
1540 /* Non-Shared-Ant */
1551 const struct rtw_chip_info *chip = rtwdev->chip;
1552 struct rtw_coex *coex = &rtwdev->coex;
1553 struct rtw_coex_stat *coex_stat = &coex->stat;
1554 struct rtw_coex_dm *coex_dm = &coex->dm;
1555 struct rtw_efuse *efuse = &rtwdev->efuse;
1561 if (efuse->share_ant)
1564 coex->freerun = true;
1573 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[0]))
1575 else if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[1]))
1577 else if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[2]))
1582 if (level > chip->wl_rf_para_num - 1)
1583 level = chip->wl_rf_para_num - 1;
1585 if (coex_stat->wl_tput_dir == COEX_WL_TPUT_TX)
1586 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_tx[level]);
1588 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[level]);
1596 const struct rtw_chip_info *chip = rtwdev->chip;
1597 struct rtw_efuse *efuse = &rtwdev->efuse;
1603 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1605 if (efuse->share_ant) {
1606 /* Shared-Ant */
1610 /* Non-Shared-Ant */
1621 const struct rtw_chip_info *chip = rtwdev->chip;
1622 struct rtw_efuse *efuse = &rtwdev->efuse;
1628 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1630 if (efuse->share_ant) {
1631 /* Shared-Ant */
1635 /* Non-Shared-Ant */
1646 const struct rtw_chip_info *chip = rtwdev->chip;
1647 struct rtw_coex *coex = &rtwdev->coex;
1648 struct rtw_coex_stat *coex_stat = &coex->stat;
1649 struct rtw_efuse *efuse = &rtwdev->efuse;
1656 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1658 if (efuse->share_ant) { /* Shared-Ant */
1659 if (coex_stat->wl_gl_busy) {
1661 if (coex_stat->bt_hid_exist &&
1662 coex_stat->bt_profile_num == 1) {
1672 } else { /* Non-Shared-Ant */
1673 if (coex_stat->wl_gl_busy)
1686 const struct rtw_chip_info *chip = rtwdev->chip;
1687 struct rtw_coex *coex = &rtwdev->coex;
1688 struct rtw_coex_stat *coex_stat = &coex->stat;
1689 struct rtw_coex_dm *coex_dm = &coex->dm;
1690 struct rtw_efuse *efuse = &rtwdev->efuse;
1691 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1695 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1697 if (coex_rfe->ant_switch_with_bt &&
1698 coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE) {
1699 if (efuse->share_ant &&
1700 COEX_RSSI_HIGH(coex_dm->wl_rssi_state[3]) &&
1701 coex_stat->wl_gl_busy) {
1704 } else if (!efuse->share_ant) {
1717 if (efuse->share_ant) {
1718 /* Shared-Ant */
1719 if (!coex_stat->wl_gl_busy) {
1722 } else if (coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE) {
1725 if (coex_stat->lo_pri_rx + coex_stat->lo_pri_tx > 250)
1734 /* Non-Shared-Ant */
1735 if (!coex_stat->wl_gl_busy) {
1738 } else if ((coex_stat->bt_ble_scan_type & 0x2) &&
1739 coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE) {
1755 const struct rtw_chip_info *chip = rtwdev->chip;
1756 struct rtw_coex *coex = &rtwdev->coex;
1757 struct rtw_coex_stat *coex_stat = &coex->stat;
1758 struct rtw_efuse *efuse = &rtwdev->efuse;
1765 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1767 if (coex_stat->wl_linkscan_proc || coex_stat->wl_hi_pri_task1 ||
1768 coex_stat->wl_hi_pri_task2)
1771 if (efuse->share_ant) {
1772 /* Shared-Ant */
1775 "[BTCoex], bt inq/page + wifi hi-pri task\n");
1778 if (coex_stat->bt_profile_num > 0)
1780 else if (coex_stat->wl_hi_pri_task1)
1782 else if (!coex_stat->bt_page)
1786 } else if (coex_stat->wl_gl_busy) {
1789 if (coex_stat->bt_profile_num == 0) {
1792 } else if (coex_stat->bt_profile_num == 1 &&
1793 !coex_stat->bt_a2dp_exist) {
1802 } else if (coex_stat->wl_connected) {
1809 "[BTCoex], bt inq/page + wifi not-connected\n");
1814 /* Non_Shared-Ant */
1817 "[BTCoex], bt inq/page + wifi hi-pri task\n");
1820 if (coex_stat->bt_profile_num > 0)
1822 else if (coex_stat->wl_hi_pri_task1)
1824 else if (!coex_stat->bt_page)
1828 } else if (coex_stat->wl_gl_busy) {
1833 } else if (coex_stat->wl_connected) {
1840 "[BTCoex], bt inq/page + wifi not-connected\n");
1847 wl_hi_pri, coex_stat->bt_page);
1855 const struct rtw_chip_info *chip = rtwdev->chip;
1856 struct rtw_coex *coex = &rtwdev->coex;
1857 struct rtw_coex_stat *coex_stat = &coex->stat;
1858 struct rtw_efuse *efuse = &rtwdev->efuse;
1859 struct rtw_coex_dm *coex_dm = &coex->dm;
1865 if (efuse->share_ant) {
1866 coex_stat->wl_coex_mode = COEX_WLINK_2GFREE;
1867 if (coex_stat->bt_whck_test)
1869 else if (coex_stat->wl_linkscan_proc || coex_stat->bt_hid_exist)
1871 else if (coex_stat->bt_setup_link || coex_stat->bt_inq_page)
1873 else if (coex_stat->bt_a2dp_exist)
1880 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[1]))
1888 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) {
1889 if (coex_stat->wl_tput_dir == COEX_WL_TPUT_TX)
1890 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_tx[6]);
1892 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[5]);
1894 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1903 const struct rtw_chip_info *chip = rtwdev->chip;
1904 struct rtw_coex *coex = &rtwdev->coex;
1905 struct rtw_coex_stat *coex_stat = &coex->stat;
1906 struct rtw_efuse *efuse = &rtwdev->efuse;
1911 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1913 if (efuse->share_ant) {
1914 /* Shared-Ant */
1918 /* Non-Shared-Ant */
1919 if (coex_stat->bt_multi_link) {
1934 const struct rtw_chip_info *chip = rtwdev->chip;
1935 struct rtw_coex *coex = &rtwdev->coex;
1936 struct rtw_coex_stat *coex_stat = &coex->stat;
1937 struct rtw_efuse *efuse = &rtwdev->efuse;
1944 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
1946 if (efuse->share_ant) {
1947 /* Shared-Ant */
1948 if (coex_stat->bt_ble_exist) {
1950 if (coex_stat->cnt_wl[COEX_CNT_WL_SCANAP] > 5) {
1959 if (coex_stat->bt_profile_num == 1 &&
1960 (coex_stat->bt_multi_link ||
1961 (coex_stat->lo_pri_rx +
1962 coex_stat->lo_pri_tx > 360) ||
1963 coex_stat->bt_slave ||
1968 } else if (coex_stat->bt_a2dp_active) {
1971 } else if (coex_stat->bt_418_hid_exist &&
1972 coex_stat->wl_gl_busy) {
1977 } else if (coex_stat->bt_ble_hid_exist &&
1978 coex_stat->wl_gl_busy) {
1987 /* Non-Shared-Ant */
1988 if (coex_stat->bt_ble_exist) {
1990 if (coex_stat->cnt_wl[COEX_CNT_WL_SCANAP] > 5) {
1997 } else if (coex_stat->bt_a2dp_active) {
2017 const struct rtw_chip_info *chip = rtwdev->chip;
2018 struct rtw_coex *coex = &rtwdev->coex;
2019 struct rtw_coex_stat *coex_stat = &coex->stat;
2020 struct rtw_coex_dm *coex_dm = &coex->dm;
2021 struct rtw_efuse *efuse = &rtwdev->efuse;
2028 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2032 if (efuse->share_ant) {
2033 /* Shared-Ant */
2034 if (coex_stat->wl_gl_busy && coex_stat->wl_noisy_level == 0)
2039 if (coex_stat->wl_connecting || !coex_stat->wl_gl_busy)
2044 /* Non-Shared-Ant */
2047 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[1]))
2059 const struct rtw_chip_info *chip = rtwdev->chip;
2060 struct rtw_coex *coex = &rtwdev->coex;
2061 struct rtw_coex_stat *coex_stat = &coex->stat;
2062 struct rtw_efuse *efuse = &rtwdev->efuse;
2069 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2071 if (efuse->share_ant) { /* Shared-Ant */
2075 } else if (coex_stat->wl_gl_busy) {
2082 } else { /* Non-Shared-Ant */
2098 const struct rtw_chip_info *chip = rtwdev->chip;
2099 struct rtw_coex *coex = &rtwdev->coex;
2100 struct rtw_coex_stat *coex_stat = &coex->stat;
2101 struct rtw_efuse *efuse = &rtwdev->efuse;
2106 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2108 if (efuse->share_ant) {
2109 /* Shared-Ant */
2110 if (coex_stat->wl_gl_busy && coex_stat->wl_noisy_level == 0)
2115 if (coex_stat->wl_gl_busy)
2120 /* Non-Shared-Ant */
2123 if (coex_stat->wl_gl_busy)
2135 const struct rtw_chip_info *chip = rtwdev->chip;
2136 struct rtw_coex *coex = &rtwdev->coex;
2137 struct rtw_coex_stat *coex_stat = &coex->stat;
2138 struct rtw_coex_dm *coex_dm = &coex->dm;
2139 struct rtw_efuse *efuse = &rtwdev->efuse;
2148 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2150 if (efuse->share_ant) {
2151 /* Shared-Ant */
2152 if (coex_stat->bt_ble_exist) {
2154 } else if (coex_stat->bt_418_hid_exist) {
2161 if (coex_stat->wl_connecting || !coex_stat->wl_gl_busy) {
2163 } else if (coex_stat->bt_418_hid_exist) {
2170 /* Non-Shared-Ant */
2171 if (coex_stat->bt_ble_exist)
2176 if (COEX_RSSI_HIGH(coex_dm->wl_rssi_state[1]))
2192 const struct rtw_chip_info *chip = rtwdev->chip;
2193 struct rtw_coex *coex = &rtwdev->coex;
2194 struct rtw_coex_stat *coex_stat = &coex->stat;
2195 struct rtw_efuse *efuse = &rtwdev->efuse;
2202 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2203 if (efuse->share_ant) {
2204 /* Shared-Ant */
2206 if (coex_stat->wl_gl_busy) {
2217 if (coex_stat->wl_gl_busy &&
2218 coex_stat->wl_noisy_level == 0)
2223 if (coex_stat->wl_gl_busy)
2229 /* Non-Shared-Ant */
2232 if (coex_stat->wl_gl_busy)
2239 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[1]);
2241 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2249 const struct rtw_chip_info *chip = rtwdev->chip;
2250 struct rtw_coex *coex = &rtwdev->coex;
2251 struct rtw_coex_stat *coex_stat = &coex->stat;
2252 struct rtw_efuse *efuse = &rtwdev->efuse;
2258 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2260 if (efuse->share_ant) {
2261 /* Shared-Ant */
2264 if (coex_stat->wl_gl_busy)
2269 /* Non-Shared-Ant */
2272 if (coex_stat->wl_gl_busy)
2284 const struct rtw_chip_info *chip = rtwdev->chip;
2285 struct rtw_coex *coex = &rtwdev->coex;
2286 struct rtw_coex_stat *coex_stat = &coex->stat;
2287 struct rtw_efuse *efuse = &rtwdev->efuse;
2292 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2294 if (efuse->share_ant) {
2295 /* Shared-Ant */
2298 if (coex_stat->wl_gl_busy)
2303 /* Non-Shared-Ant */
2306 if (coex_stat->wl_gl_busy)
2318 const struct rtw_chip_info *chip = rtwdev->chip;
2319 struct rtw_coex *coex = &rtwdev->coex;
2320 struct rtw_efuse *efuse = &rtwdev->efuse;
2321 struct rtw_coex_stat *coex_stat = &coex->stat;
2327 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2331 if (coex_stat->bt_game_hid_exist && coex_stat->wl_linkscan_proc)
2332 coex_stat->wl_coex_mode = COEX_WLINK_2GFREE;
2334 if (efuse->share_ant) {
2335 /* Shared-Ant */
2339 /* Non-Shared-Ant */
2350 const struct rtw_chip_info *chip = rtwdev->chip;
2351 struct rtw_efuse *efuse = &rtwdev->efuse;
2356 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2358 if (efuse->share_ant) {
2359 /* Shared-Ant */
2363 /* Non-Shared-Ant */
2374 const struct rtw_chip_info *chip = rtwdev->chip;
2375 struct rtw_coex *coex = &rtwdev->coex;
2376 struct rtw_efuse *efuse = &rtwdev->efuse;
2377 struct rtw_coex_stat *coex_stat = &coex->stat;
2380 if (coex->under_5g)
2387 if (efuse->share_ant) {
2388 /* Shared-Ant */
2392 /* Non-Shared-Ant */
2397 if (coex_stat->bt_game_hid_exist) {
2398 coex_stat->wl_coex_mode = COEX_WLINK_2GFREE;
2399 if (coex_stat->wl_tput_dir == COEX_WL_TPUT_TX)
2400 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_tx[6]);
2402 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[5]);
2404 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2413 const struct rtw_chip_info *chip = rtwdev->chip;
2414 struct rtw_coex *coex = &rtwdev->coex;
2415 struct rtw_coex_stat *coex_stat = &coex->stat;
2416 struct rtw_efuse *efuse = &rtwdev->efuse;
2422 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2424 if (efuse->share_ant) { /* Shared-Ant */
2425 if (coex_stat->bt_a2dp_exist) {
2428 if (coex_stat->wl_gl_busy)
2436 } else { /* Non-Shared-Ant */
2437 if (coex_stat->bt_a2dp_exist) {
2453 const struct rtw_chip_info *chip = rtwdev->chip;
2454 struct rtw_efuse *efuse = &rtwdev->efuse;
2459 rtw_coex_set_rf_para(rtwdev, chip->wl_rf_para_rx[0]);
2461 if (efuse->share_ant) {
2462 /* Shared-Ant */
2466 /* Non-Shared-Ant */
2477 struct rtw_coex *coex = &rtwdev->coex;
2478 struct rtw_coex_stat *coex_stat = &coex->stat;
2498 else if (coex_stat->bt_a2dp_sink)
2530 const struct rtw_chip_info *chip = rtwdev->chip;
2531 struct rtw_coex *coex = &rtwdev->coex;
2532 struct rtw_coex_dm *coex_dm = &coex->dm;
2533 struct rtw_coex_stat *coex_stat = &coex->stat;
2536 lockdep_assert_held(&rtwdev->mutex);
2538 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
2541 coex_dm->reason = reason;
2551 if (coex->manual_control) {
2557 if (coex->stop_dm) {
2563 if (coex_stat->wl_under_ips) {
2569 if (coex->freeze && coex_dm->reason == COEX_RSN_BTINFO &&
2570 !coex_stat->bt_setup_link) {
2576 coex_stat->cnt_wl[COEX_CNT_WL_COEXRUN]++;
2577 coex->freerun = false;
2579 /* Pure-5G Coex Process */
2580 if (coex->under_5g) {
2581 coex_stat->wl_coex_mode = COEX_WLINK_5G;
2586 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], WiFi is single-port 2G!!\n");
2587 coex_stat->wl_coex_mode = COEX_WLINK_2G1PORT;
2589 if (coex_stat->bt_disabled) {
2590 if (coex_stat->wl_connected && rf4ce_en)
2592 else if (!coex_stat->wl_connected)
2599 if (coex_stat->wl_under_lps && !coex_stat->wl_force_lps_ctrl) {
2604 if (coex_stat->bt_game_hid_exist && coex_stat->wl_connected) {
2609 if (coex_stat->bt_whck_test) {
2614 if (coex_stat->bt_setup_link) {
2619 if (coex_stat->bt_inq_page) {
2624 if ((coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE ||
2625 coex_dm->bt_status == COEX_BTSTATUS_CON_IDLE) &&
2626 coex_stat->wl_connected) {
2631 if (coex_stat->wl_linkscan_proc && !coex->freerun) {
2636 if (coex_stat->wl_connected) {
2646 if (chip->wl_mimo_ps_support) {
2647 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) {
2648 if (coex_dm->reason == COEX_RSN_2GMEDIA)
2657 rtw_coex_gnt_workaround(rtwdev, false, coex_stat->wl_coex_mode);
2663 struct rtw_coex *coex = &rtwdev->coex;
2664 struct rtw_coex_stat *coex_stat = &coex->stat;
2665 struct rtw_coex_dm *coex_dm = &coex->dm;
2672 coex_stat->cnt_wl[i] = 0;
2675 coex_stat->cnt_bt[i] = 0;
2677 for (i = 0; i < ARRAY_SIZE(coex_dm->bt_rssi_state); i++)
2678 coex_dm->bt_rssi_state[i] = COEX_RSSI_STATE_LOW;
2680 for (i = 0; i < ARRAY_SIZE(coex_dm->wl_rssi_state); i++)
2681 coex_dm->wl_rssi_state[i] = COEX_RSSI_STATE_LOW;
2683 coex_stat->wl_coex_mode = COEX_WLINK_MAX;
2684 coex_stat->wl_rx_rate = DESC_RATE5_5M;
2685 coex_stat->wl_rts_rx_rate = DESC_RATE5_5M;
2690 struct rtw_coex *coex = &rtwdev->coex;
2691 struct rtw_coex_stat *coex_stat = &coex->stat;
2697 coex_stat->kt_ver = u8_get_bits(rtw_read8(rtwdev, 0xf1), GENMASK(7, 4));
2700 rtw_coex_wl_slot_extend(rtwdev, coex_stat->wl_slot_extend);
2707 /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */
2710 /* set Tx beacon = Hi-Pri */
2713 /* set Tx beacon queue = Hi-Pri */
2717 if (coex->wl_rf_off) {
2720 coex->stop_dm = true;
2728 coex->stop_dm = true;
2733 coex->stop_dm = false;
2734 coex->freeze = true;
2745 struct rtw_coex *coex = &rtwdev->coex;
2750 coex->stop_dm = true;
2751 coex->wl_rf_off = false;
2760 /* set antenna path to BT */
2781 struct rtw_coex *coex = &rtwdev->coex;
2782 struct rtw_coex_stat *coex_stat = &coex->stat;
2784 if (coex->manual_control || coex->stop_dm)
2790 coex_stat->wl_under_ips = true;
2804 coex_stat->wl_under_ips = false;
2810 struct rtw_coex *coex = &rtwdev->coex;
2811 struct rtw_coex_stat *coex_stat = &coex->stat;
2813 if (coex->manual_control || coex->stop_dm)
2819 coex_stat->wl_under_lps = true;
2821 if (coex_stat->wl_force_lps_ctrl) {
2822 /* for ps-tdma */
2834 coex_stat->wl_under_lps = false;
2839 if (!coex_stat->wl_force_lps_ctrl)
2848 struct rtw_coex *coex = &rtwdev->coex;
2849 struct rtw_coex_stat *coex_stat = &coex->stat;
2851 if (coex->manual_control || coex->stop_dm)
2854 coex->freeze = false;
2867 coex_stat->wl_hi_pri_task2 = true;
2873 coex_stat->cnt_wl[COEX_CNT_WL_SCANAP] = 30; /* To do */
2876 "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n",
2877 coex_stat->cnt_wl[COEX_CNT_WL_SCANAP]);
2879 coex_stat->wl_hi_pri_task2 = false;
2886 struct rtw_coex *coex = &rtwdev->coex;
2888 if (coex->manual_control || coex->stop_dm)
2912 struct rtw_coex *coex = &rtwdev->coex;
2913 struct rtw_coex_stat *coex_stat = &coex->stat;
2915 if (coex->manual_control || coex->stop_dm)
2933 coex_stat->wl_hi_pri_task1 = true;
2934 coex_stat->wl_connecting = true;
2935 coex_stat->cnt_wl[COEX_CNT_WL_CONNPKT] = 2;
2936 coex_stat->wl_connecting = true;
2937 ieee80211_queue_delayed_work(rtwdev->hw,
2938 &coex->wl_connecting_work, 2 * HZ);
2947 /* To keep TDMA case during connect process,
2948 * to avoid changed by Btinfo and runcoexmechanism
2950 coex->freeze = true;
2951 ieee80211_queue_delayed_work(rtwdev->hw, &coex->defreeze_work,
2954 coex_stat->wl_hi_pri_task1 = false;
2955 coex->freeze = false;
2956 coex_stat->wl_connecting = false;
2966 struct rtw_coex *coex = &rtwdev->coex;
2967 struct rtw_coex_stat *coex_stat = &coex->stat;
2969 if (coex->manual_control || coex->stop_dm)
2982 coex_stat->wl_connecting = false;
3004 const struct rtw_chip_info *chip = rtwdev->chip;
3005 struct rtw_coex *coex = &rtwdev->coex;
3006 struct rtw_coex_stat *coex_stat = &coex->stat;
3007 struct rtw_coex_dm *coex_dm = &coex->dm;
3015 coex_stat->cnt_bt_info_c2h[rsp_source]++;
3018 coex_stat->bt_iqk_state = buf[1];
3019 if (coex_stat->bt_iqk_state == 0)
3020 coex_stat->cnt_bt[COEX_CNT_BT_IQK]++;
3021 else if (coex_stat->bt_iqk_state == 2)
3022 coex_stat->cnt_bt[COEX_CNT_BT_IQKFAIL]++;
3037 if (coex_stat->bt_disabled != coex_stat->bt_disabled_pre) {
3038 coex_stat->bt_disabled_pre = coex_stat->bt_disabled;
3050 coex_dm->fw_tdma_para[i - 1] = buf[i];
3064 if (coex_stat->bt_disabled) {
3065 coex_stat->bt_disabled = false;
3066 coex_stat->bt_reenable = true;
3067 ieee80211_queue_delayed_work(rtwdev->hw,
3068 &coex->bt_reenable_work,
3087 coex_stat->bt_info_c2h[rsp_source][i] = buf[i];
3090 if (coex_stat->bt_info_c2h[rsp_source][1] == coex_stat->bt_info_lb2 &&
3091 coex_stat->bt_info_c2h[rsp_source][2] == coex_stat->bt_info_lb3 &&
3092 coex_stat->bt_info_c2h[rsp_source][3] == coex_stat->bt_info_hb0 &&
3093 coex_stat->bt_info_c2h[rsp_source][4] == coex_stat->bt_info_hb1 &&
3094 coex_stat->bt_info_c2h[rsp_source][5] == coex_stat->bt_info_hb2 &&
3095 coex_stat->bt_info_c2h[rsp_source][6] == coex_stat->bt_info_hb3) {
3101 coex_stat->bt_info_lb2 = coex_stat->bt_info_c2h[rsp_source][1];
3102 coex_stat->bt_info_lb3 = coex_stat->bt_info_c2h[rsp_source][2];
3103 coex_stat->bt_info_hb0 = coex_stat->bt_info_c2h[rsp_source][3];
3104 coex_stat->bt_info_hb1 = coex_stat->bt_info_c2h[rsp_source][4];
3105 coex_stat->bt_info_hb2 = coex_stat->bt_info_c2h[rsp_source][5];
3106 coex_stat->bt_info_hb3 = coex_stat->bt_info_c2h[rsp_source][6];
3109 coex_stat->bt_whck_test = (coex_stat->bt_info_lb2 == 0xff);
3111 inq_page = ((coex_stat->bt_info_lb2 & BIT(2)) == BIT(2));
3113 if (inq_page != coex_stat->bt_inq_page) {
3114 cancel_delayed_work_sync(&coex->bt_remain_work);
3115 coex_stat->bt_inq_page = inq_page;
3118 coex_stat->bt_inq_remain = true;
3120 ieee80211_queue_delayed_work(rtwdev->hw,
3121 &coex->bt_remain_work,
3124 coex_stat->bt_acl_busy = ((coex_stat->bt_info_lb2 & BIT(3)) == BIT(3));
3125 if (chip->ble_hid_profile_support) {
3126 if (coex_stat->bt_info_lb2 & BIT(5)) {
3127 if (coex_stat->bt_info_hb1 & BIT(0)) {
3129 coex_stat->bt_ble_hid_exist = true;
3131 coex_stat->bt_ble_hid_exist = false;
3133 coex_stat->bt_ble_exist = false;
3134 } else if (coex_stat->bt_info_hb1 & BIT(0)) {
3136 coex_stat->bt_ble_hid_exist = false;
3137 coex_stat->bt_ble_exist = true;
3139 coex_stat->bt_ble_hid_exist = false;
3140 coex_stat->bt_ble_exist = false;
3143 if (coex_stat->bt_info_hb1 & BIT(0)) {
3144 if (coex_stat->bt_hid_slot == 1 &&
3145 coex_stat->hi_pri_rx + 100 < coex_stat->hi_pri_tx &&
3146 coex_stat->hi_pri_rx < 100) {
3147 coex_stat->bt_ble_hid_exist = true;
3148 coex_stat->bt_ble_exist = false;
3150 coex_stat->bt_ble_hid_exist = false;
3151 coex_stat->bt_ble_exist = true;
3154 coex_stat->bt_ble_hid_exist = false;
3155 coex_stat->bt_ble_exist = false;
3159 coex_stat->cnt_bt[COEX_CNT_BT_RETRY] = coex_stat->bt_info_lb3 & 0xf;
3160 if (coex_stat->cnt_bt[COEX_CNT_BT_RETRY] >= 1)
3161 coex_stat->cnt_bt[COEX_CNT_BT_POPEVENT]++;
3163 coex_stat->bt_fix_2M = ((coex_stat->bt_info_lb3 & BIT(4)) == BIT(4));
3164 coex_stat->bt_inq = ((coex_stat->bt_info_lb3 & BIT(5)) == BIT(5));
3165 if (coex_stat->bt_inq)
3166 coex_stat->cnt_bt[COEX_CNT_BT_INQ]++;
3168 coex_stat->bt_page = ((coex_stat->bt_info_lb3 & BIT(7)) == BIT(7));
3169 if (coex_stat->bt_page)
3170 coex_stat->cnt_bt[COEX_CNT_BT_PAGE]++;
3172 /* unit: % (value-100 to translate to unit: dBm in coex info) */
3173 if (chip->bt_rssi_type == COEX_BTRSSI_RATIO) {
3174 coex_stat->bt_rssi = coex_stat->bt_info_hb0 * 2 + 10;
3176 if (coex_stat->bt_info_hb0 <= 127)
3177 coex_stat->bt_rssi = 100;
3178 else if (256 - coex_stat->bt_info_hb0 <= 100)
3179 coex_stat->bt_rssi = 100 - (256 - coex_stat->bt_info_hb0);
3181 coex_stat->bt_rssi = 0;
3184 if (coex_stat->bt_info_hb1 & BIT(1))
3185 coex_stat->cnt_bt[COEX_CNT_BT_REINIT]++;
3187 if (coex_stat->bt_info_hb1 & BIT(2)) {
3188 coex_stat->cnt_bt[COEX_CNT_BT_SETUPLINK]++;
3189 coex_stat->bt_setup_link = true;
3190 if (coex_stat->bt_reenable)
3195 ieee80211_queue_delayed_work(rtwdev->hw,
3196 &coex->bt_relink_work,
3200 "[BTCoex], Re-Link start in BT info!!\n");
3203 if (coex_stat->bt_info_hb1 & BIT(3))
3204 coex_stat->cnt_bt[COEX_CNT_BT_IGNWLANACT]++;
3206 coex_stat->bt_ble_voice = ((coex_stat->bt_info_hb1 & BIT(4)) == BIT(4));
3207 coex_stat->bt_ble_scan_en = ((coex_stat->bt_info_hb1 & BIT(5)) == BIT(5));
3208 if (coex_stat->bt_info_hb1 & BIT(6))
3209 coex_stat->cnt_bt[COEX_CNT_BT_ROLESWITCH]++;
3211 coex_stat->bt_multi_link = ((coex_stat->bt_info_hb1 & BIT(7)) == BIT(7));
3213 /* Use PS-TDMA to protect WL RX */
3214 if (!coex_stat->bt_multi_link && coex_stat->bt_multi_link_pre) {
3215 coex_stat->bt_multi_link_remain = true;
3216 ieee80211_queue_delayed_work(rtwdev->hw,
3217 &coex->bt_multi_link_remain_work,
3220 coex_stat->bt_multi_link_pre = coex_stat->bt_multi_link;
3222 /* resend wifi info to bt, it is reset and lost the info */
3223 if (coex_stat->bt_info_hb1 & BIT(1)) {
3225 "[BTCoex], BT Re-init, send wifi BW & Chnl to BT!!\n");
3227 if (coex_stat->wl_connected)
3235 if ((coex_stat->bt_info_hb1 & BIT(3)) &&
3236 (!(coex_stat->bt_info_hb1 & BIT(2)))) {
3238 "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n");
3242 coex_stat->bt_opp_exist = ((coex_stat->bt_info_hb2 & BIT(0)) == BIT(0));
3243 if (coex_stat->bt_info_hb2 & BIT(1))
3244 coex_stat->cnt_bt[COEX_CNT_BT_AFHUPDATE]++;
3246 coex_stat->bt_a2dp_active = (coex_stat->bt_info_hb2 & BIT(2)) == BIT(2);
3247 coex_stat->bt_slave = ((coex_stat->bt_info_hb2 & BIT(3)) == BIT(3));
3248 coex_stat->bt_hid_slot = (coex_stat->bt_info_hb2 & 0x30) >> 4;
3249 coex_stat->bt_hid_pair_num = (coex_stat->bt_info_hb2 & 0xc0) >> 6;
3250 if (coex_stat->bt_hid_pair_num > 0 && coex_stat->bt_hid_slot >= 2)
3251 coex_stat->bt_418_hid_exist = true;
3252 else if (coex_stat->bt_hid_pair_num == 0 || coex_stat->bt_hid_slot == 1)
3253 coex_stat->bt_418_hid_exist = false;
3255 if ((coex_stat->bt_info_lb2 & 0x49) == 0x49)
3256 coex_stat->bt_a2dp_bitpool = (coex_stat->bt_info_hb3 & 0x7f);
3258 coex_stat->bt_a2dp_bitpool = 0;
3260 coex_stat->bt_a2dp_sink = ((coex_stat->bt_info_hb3 & BIT(7)) == BIT(7));
3272 const struct rtw_chip_info *chip = rtwdev->chip;
3273 struct rtw_coex *coex = &rtwdev->coex;
3274 struct rtw_coex_stat *coex_stat = &coex->stat;
3281 if (!chip->wl_mimo_ps_support &&
3290 hl = &coex_stat->hid_handle_list;
3294 coex_stat->hid_handle_list = *bhl;
3295 memset(&coex_stat->hid_info, 0, sizeof(coex_stat->hid_info));
3297 hidinfo = &coex_stat->hid_info[i];
3298 if (hl->handle[i] != COEX_BT_HIDINFO_NOTCON &&
3299 hl->handle[i] != 0)
3300 hidinfo->hid_handle = hl->handle[i];
3305 handle = hida->handle;
3307 hidinfo = &coex_stat->hid_info[i];
3308 if (hidinfo->hid_handle == handle) {
3309 hidinfo->hid_vendor = hida->vendor;
3310 memcpy(hidinfo->hid_name, hida->name,
3311 sizeof(hidinfo->hid_name));
3312 hidinfo->hid_info_completed = true;
3319 hidinfo = &coex_stat->hid_info[i];
3320 complete = hidinfo->hid_info_completed;
3321 handle = hidinfo->hid_handle;
3324 hidinfo->is_game_hid = false;
3328 if (hidinfo->hid_vendor == COEX_BT_HIDINFO_MTK) {
3329 if ((memcmp(hidinfo->hid_name,
3332 hidinfo->is_game_hid = true;
3333 else if ((memcmp(hidinfo->hid_name,
3336 hidinfo->is_game_hid = true;
3338 hidinfo->is_game_hid = false;
3340 hidinfo->is_game_hid = false;
3342 if (hidinfo->is_game_hid)
3351 if (cur_game_hid_exist != coex_stat->bt_game_hid_exist) {
3352 coex_stat->bt_game_hid_exist = cur_game_hid_exist;
3355 coex_stat->bt_game_hid_exist);
3362 const struct rtw_chip_info *chip = rtwdev->chip;
3363 struct rtw_coex *coex = &rtwdev->coex;
3364 struct rtw_coex_stat *coex_stat = &coex->stat;
3369 if (!chip->wl_mimo_ps_support || coex_stat->wl_under_ips ||
3370 (coex_stat->wl_under_lps && !coex_stat->wl_force_lps_ctrl))
3373 if (!coex_stat->bt_hid_exist &&
3374 !((coex_stat->bt_info_lb2 & COEX_INFO_CONNECTION) &&
3375 (coex_stat->hi_pri_tx + coex_stat->hi_pri_rx >
3382 hidinfo = &coex_stat->hid_info[i];
3383 complete = hidinfo->hid_info_completed;
3384 handle = hidinfo->hid_handle;
3397 struct rtw_coex *coex = &rtwdev->coex;
3398 struct rtw_coex_stat *coex_stat = &coex->stat;
3412 val = coex_stat->wl_fw_dbg_info_pre[i];
3414 coex_stat->wl_fw_dbg_info[i] = buf[i] - val;
3416 coex_stat->wl_fw_dbg_info[i] = 255 - val + buf[i];
3418 coex_stat->wl_fw_dbg_info_pre[i] = buf[i];
3421 coex_stat->cnt_wl[COEX_CNT_WL_FW_NOTIFY]++;
3433 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3435 if ((coex_stat->wl_under_lps && !coex_stat->wl_force_lps_ctrl) ||
3436 coex_stat->wl_under_ips)
3446 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3448 mutex_lock(&rtwdev->mutex);
3449 coex_stat->bt_setup_link = false;
3451 mutex_unlock(&rtwdev->mutex);
3458 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3460 mutex_lock(&rtwdev->mutex);
3461 coex_stat->bt_reenable = false;
3462 mutex_unlock(&rtwdev->mutex);
3469 struct rtw_coex *coex = &rtwdev->coex;
3470 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3472 mutex_lock(&rtwdev->mutex);
3473 coex->freeze = false;
3474 coex_stat->wl_hi_pri_task1 = false;
3476 mutex_unlock(&rtwdev->mutex);
3483 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3485 mutex_lock(&rtwdev->mutex);
3486 coex_stat->wl_gl_busy = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
3488 mutex_unlock(&rtwdev->mutex);
3495 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3497 mutex_lock(&rtwdev->mutex);
3498 coex_stat->bt_inq_remain = coex_stat->bt_inq_page;
3500 mutex_unlock(&rtwdev->mutex);
3507 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3509 mutex_lock(&rtwdev->mutex);
3510 coex_stat->wl_connecting = false;
3513 mutex_unlock(&rtwdev->mutex);
3520 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3522 mutex_lock(&rtwdev->mutex);
3523 coex_stat->bt_multi_link_remain = false;
3524 mutex_unlock(&rtwdev->mutex);
3531 struct rtw_coex_stat *coex_stat = &rtwdev->coex.stat;
3533 mutex_lock(&rtwdev->mutex);
3534 coex_stat->wl_cck_lock = false;
3535 mutex_unlock(&rtwdev->mutex);
3584 const struct rtw_chip_info *chip = rtwdev->chip;
3585 struct rtw_efuse *efuse = &rtwdev->efuse;
3590 bool share_ant = efuse->share_ant;
3593 n = chip->table_sant_num;
3595 n = chip->table_nsant_num;
3599 load_bt_val = chip->table_sant[i].bt;
3600 load_wl_val = chip->table_sant[i].wl;
3602 load_bt_val = chip->table_nsant[i].bt;
3603 load_wl_val = chip->table_nsant[i].wl;
3620 const struct rtw_chip_info *chip = rtwdev->chip;
3621 struct rtw_efuse *efuse = &rtwdev->efuse;
3626 bool share_ant = efuse->share_ant;
3629 n = chip->tdma_sant_num;
3631 n = chip->tdma_nsant_num;
3637 load_cur_tab_val = chip->tdma_sant[i].para[j];
3639 load_cur_tab_val = chip->tdma_nsant[i].para[j];
3665 if (INFO_SIZE - n <= 0)
3668 switch (reg->domain) {
3687 ffs = __ffs(reg->mask);
3688 fls = __fls(reg->mask);
3691 return scnprintf(addr_info + n, INFO_SIZE - n, "%s%s%x",
3692 sep, rf_prefix, reg->addr);
3694 return scnprintf(addr_info + n, INFO_SIZE - n, "%s%s%x[%d]",
3695 sep, rf_prefix, reg->addr, ffs);
3697 return scnprintf(addr_info + n, INFO_SIZE - n, "%s%s%x[%d:%d]",
3698 sep, rf_prefix, reg->addr, fls, ffs);
3708 if (INFO_SIZE - n <= 0)
3711 switch (reg->domain) {
3713 return scnprintf(val_info + n, INFO_SIZE - n, "%s0x%x", sep,
3714 rtw_read32_mask(rtwdev, reg->addr, reg->mask));
3716 return scnprintf(val_info + n, INFO_SIZE - n, "%s0x%x", sep,
3717 rtw_read16_mask(rtwdev, reg->addr, reg->mask));
3719 return scnprintf(val_info + n, INFO_SIZE - n, "%s0x%x", sep,
3720 rtw_read8_mask(rtwdev, reg->addr, reg->mask));
3732 return scnprintf(val_info + n, INFO_SIZE - n, "%s0x%x", sep,
3733 rtw_read_rf(rtwdev, rf_path, reg->addr, reg->mask));
3738 const struct rtw_chip_info *chip = rtwdev->chip;
3746 for (i = 0; i < chip->coex_info_hw_regs_num; i++) {
3747 reg = &chip->coex_info_hw_regs[i];
3752 if (reg->domain == RTW_REG_DOMAIN_NL) {
3753 seq_printf(m, "%-40s = %s\n", addr_info, val_info);
3760 seq_printf(m, "%-40s = %s\n", addr_info, val_info);
3854 struct rtw_vif *rtwvif = sta_iter_data->rtwvif;
3855 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
3856 struct seq_file *m = sta_iter_data->file;
3860 if (si->vif != vif)
3863 rssi = ewma_rssi_read(&si->avg_rssi);
3864 seq_printf(m, "\tPeer %3d\n", si->mac_id);
3865 seq_printf(m, "\t\t%-24s = %d\n", "RSSI", rssi);
3866 seq_printf(m, "\t\t%-24s = %d\n", "BW mode", si->bw_mode);
3879 struct rtw_dev *rtwdev = vif_iter_data->rtwdev;
3880 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
3881 struct seq_file *m = vif_iter_data->file;
3882 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
3884 seq_printf(m, "Iface on Port (%d)\n", rtwvif->port);
3885 seq_printf(m, "\t%-32s = %d\n",
3886 "Beacon interval", bss_conf->beacon_int);
3887 seq_printf(m, "\t%-32s = %d\n",
3888 "Network Type", rtwvif->net_type);
3912 const struct rtw_chip_info *chip = rtwdev->chip;
3913 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3914 struct rtw_coex *coex = &rtwdev->coex;
3915 struct rtw_coex_stat *coex_stat = &coex->stat;
3916 struct rtw_coex_dm *coex_dm = &coex->dm;
3917 struct rtw_hal *hal = &rtwdev->hal;
3918 struct rtw_efuse *efuse = &rtwdev->efuse;
3919 struct rtw_fw_state *fw = &rtwdev->fw;
3921 u8 reason = coex_dm->reason;
3929 score_board_WB = coex_stat->score_board;
3940 if (!coex_stat->wl_under_ips &&
3941 (!coex_stat->wl_under_lps || coex_stat->wl_force_lps_ctrl) &&
3942 !coex_stat->bt_disabled && !coex_stat->bt_mailbox_reply) {
3944 &coex_stat->bt_supported_version);
3945 rtw_coex_get_bt_patch_version(rtwdev, &coex_stat->patch_ver);
3947 &coex_stat->bt_supported_feature);
3948 rtw_coex_get_bt_reg(rtwdev, 3, 0xae, &coex_stat->bt_reg_vendor_ae);
3949 rtw_coex_get_bt_reg(rtwdev, 3, 0xac, &coex_stat->bt_reg_vendor_ac);
3951 if (coex_stat->patch_ver != 0)
3952 coex_stat->bt_mailbox_reply = true;
3957 seq_printf(m, "\t\tBT Coexist info %x\n", chip->id);
3960 if (coex->manual_control) {
3964 } else if (coex->stop_dm) {
3968 } else if (coex->freeze) {
3973 seq_printf(m, "%-40s = %s/ %d\n",
3975 efuse->share_ant ? "Shared" : "Non-Shared",
3976 efuse->rfe_option);
3977 seq_printf(m, "%-40s = %08x/ 0x%02x/ 0x%08x %s\n",
3979 chip->coex_para_ver, chip->bt_desired_ver,
3980 coex_stat->bt_supported_version,
3981 coex_stat->bt_disabled ? "(BT disabled)" :
3982 coex_stat->bt_supported_version >= chip->bt_desired_ver ?
3984 seq_printf(m, "%-40s = %s/ %u/ %d\n",
3986 coex_stat->bt_slave ? "Slave" : "Master",
3987 coex_stat->cnt_bt[COEX_CNT_BT_ROLESWITCH],
3988 coex_dm->ignore_wl_act);
3989 seq_printf(m, "%-40s = %u.%u/ 0x%x/ 0x%x/ %c\n",
3991 fw->version, fw->sub_version,
3992 coex_stat->patch_ver,
3993 chip->wl_fw_desired_ver, coex_stat->kt_ver + 65);
3994 seq_printf(m, "%-40s = %u/ %u/ %u/ ch-(%u)\n",
3996 coex_dm->wl_ch_info[0], coex_dm->wl_ch_info[1],
3997 coex_dm->wl_ch_info[2], hal->current_channel);
4003 seq_printf(m, "%-40s = %s/ %ddBm/ %u/ %u\n",
4005 coex_dm->bt_status == COEX_BTSTATUS_NCON_IDLE ? "non-conn" :
4006 coex_dm->bt_status == COEX_BTSTATUS_CON_IDLE ? "conn-idle" : "busy",
4007 coex_stat->bt_rssi - 100,
4008 coex_stat->cnt_bt[COEX_CNT_BT_RETRY],
4009 coex_stat->cnt_bt[COEX_CNT_BT_POPEVENT]);
4010 seq_printf(m, "%-40s = %s%s%s%s%s (multi-link %d)\n",
4012 coex_stat->bt_a2dp_exist ? (coex_stat->bt_a2dp_sink ?
4014 coex_stat->bt_hfp_exist ? "HFP," : "",
4015 coex_stat->bt_hid_exist ?
4016 (coex_stat->bt_ble_exist ? "HID(RCU)," :
4017 coex_stat->bt_hid_slot >= 2 ? "HID(4/18)" :
4018 coex_stat->bt_ble_hid_exist ? "HID(BLE)" :
4020 coex_stat->bt_pan_exist ? coex_stat->bt_opp_exist ?
4022 coex_stat->bt_ble_voice ? "Voice," : "",
4023 coex_stat->bt_multi_link);
4024 seq_printf(m, "%-40s = %u/ %u/ %u/ 0x%08x\n",
4026 coex_stat->cnt_bt[COEX_CNT_BT_REINIT],
4027 coex_stat->cnt_bt[COEX_CNT_BT_SETUPLINK],
4028 coex_stat->cnt_bt[COEX_CNT_BT_IGNWLANACT],
4029 coex_stat->bt_supported_feature);
4030 seq_printf(m, "%-40s = %u/ %u/ %u/ %u\n",
4032 coex_stat->cnt_bt[COEX_CNT_BT_PAGE],
4033 coex_stat->cnt_bt[COEX_CNT_BT_INQ],
4034 coex_stat->cnt_bt[COEX_CNT_BT_IQK],
4035 coex_stat->cnt_bt[COEX_CNT_BT_IQKFAIL]);
4036 seq_printf(m, "%-40s = 0x%04x/ 0x%04x/ 0x%04x/ 0x%04x\n",
4037 "0xae/ 0xac/ score board (W->B)/ (B->W)",
4038 coex_stat->bt_reg_vendor_ae,
4039 coex_stat->bt_reg_vendor_ac,
4041 seq_printf(m, "%-40s = %u/%u, %u/%u\n",
4042 "Hi-Pri TX/RX, Lo-Pri TX/RX",
4043 coex_stat->hi_pri_tx, coex_stat->hi_pri_rx,
4044 coex_stat->lo_pri_tx, coex_stat->lo_pri_rx);
4046 seq_printf(m, "%-40s = %7ph\n",
4048 coex_stat->bt_info_c2h[i]);
4053 seq_printf(m, "%-40s = %d\n",
4054 "Scanning", test_bit(RTW_FLAG_SCANNING, rtwdev->flags));
4055 seq_printf(m, "%-40s = %u/ TX %d Mbps/ RX %d Mbps\n",
4057 coex_stat->wl_gl_busy,
4058 rtwdev->stats.tx_throughput, rtwdev->stats.rx_throughput);
4059 seq_printf(m, "%-40s = %u/ %u/ %u\n",
4061 !test_bit(RTW_FLAG_POWERON, rtwdev->flags),
4062 test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags),
4063 rtwdev->lps_conf.mode);
4069 if (coex->manual_control) {
4073 seq_printf(m, "%-40s = %5ph (%d)\n",
4075 coex_dm->fw_tdma_para,
4077 &coex_dm->fw_tdma_para[0]));
4082 seq_printf(m, "%-40s = %5ph (case-%d)\n",
4084 coex_dm->ps_tdma_para, coex_dm->cur_ps_tdma);
4086 seq_printf(m, "%-40s = %s/ %s/ %d\n",
4088 rtw_coex_get_wl_coex_mode(coex_stat->wl_coex_mode),
4089 coex->freerun ? "Yes" : "No",
4090 coex_stat->tdma_timer_base);
4091 seq_printf(m, "%-40s = %d(%d)/ 0x%08x/ 0x%08x/ 0x%08x\n",
4093 coex_dm->cur_table,
4096 seq_printf(m, "%-40s = 0x%08x/ 0x%08x/ %d/ reason (%s)\n",
4099 coex_stat->cnt_wl[COEX_CNT_WL_COEXRUN],
4101 seq_printf(m, "%-40s = %3ph\n",
4102 "AFH Map to BT",
4103 coex_dm->wl_ch_info);
4104 seq_printf(m, "%-40s = %s/ %d\n",
4106 coex_stat->wl_force_lps_ctrl ? "On" : "Off",
4107 coex_stat->wl_gl_busy);
4108 seq_printf(m, "%-40s = %u/ %u/ %u/ %u/ %u\n",
4110 coex_stat->wl_fw_dbg_info[1], coex_stat->wl_fw_dbg_info[2],
4111 coex_stat->wl_fw_dbg_info[3], coex_stat->wl_fw_dbg_info[4],
4112 coex_stat->wl_fw_dbg_info[5]);
4113 seq_printf(m, "%-40s = %u/ %u/ %s/ %u\n",
4115 coex_stat->wl_fw_dbg_info[6],
4116 coex_stat->wl_fw_dbg_info[7],
4117 coex_stat->wl_slot_extend ? "Yes" : "No",
4118 coex_stat->cnt_wl[COEX_CNT_WL_FW_NOTIFY]);
4119 seq_printf(m, "%-40s = %d/ %d/ %s/ %d\n",
4121 coex_dm->cur_wl_pwr_lvl,
4122 coex_dm->cur_bt_pwr_lvl,
4123 coex_dm->cur_wl_rx_low_gain_en ? "On" : "Off",
4124 coex_dm->cur_bt_lna_lvl);
4129 seq_printf(m, "%-40s = %s/ %s\n",
4133 seq_printf(m, "%-40s = RF:%s_BB:%s/ RF:%s_BB:%s/ %s\n",
4140 seq_printf(m, "%-40s = %lu/ %lu\n",
4143 seq_printf(m, "%-40s = %u/ %u/ %u/ %u\n",
4145 dm_info->cck_ok_cnt, dm_info->ofdm_ok_cnt,
4146 dm_info->ht_ok_cnt, dm_info->vht_ok_cnt);
4147 seq_printf(m, "%-40s = %u/ %u/ %u/ %u\n",
4149 dm_info->cck_err_cnt, dm_info->ofdm_err_cnt,
4150 dm_info->ht_err_cnt, dm_info->vht_err_cnt);
4151 seq_printf(m, "%-40s = %s/ %s/ %s/ %u\n",
4153 coex_stat->wl_hi_pri_task1 ? "Y" : "N",
4154 coex_stat->wl_cck_lock ? "Y" : "N",
4155 coex_stat->wl_cck_lock_ever ? "Y" : "N",
4156 coex_stat->wl_noisy_level);
4159 seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n",
4161 -dm_info->rx_evm_dbm[RF_PATH_A],
4162 -dm_info->rx_evm_dbm[RF_PATH_B],
4163 -dm_info->rx_snr[RF_PATH_A],
4164 -dm_info->rx_snr[RF_PATH_B]);
4165 seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n",
4166 "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA",
4167 dm_info->cck_cca_cnt, dm_info->cck_fa_cnt,
4168 dm_info->ofdm_cca_cnt, dm_info->ofdm_fa_cnt);
4169 seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n", "CRC OK CCK/11g/11n/11ac",
4170 dm_info->cck_ok_cnt, dm_info->ofdm_ok_cnt,
4171 dm_info->ht_ok_cnt, dm_info->vht_ok_cnt);
4172 seq_printf(m, "%-40s = %d/ %d/ %d/ %d\n", "CRC Err CCK/11g/11n/11ac",
4173 dm_info->cck_err_cnt, dm_info->ofdm_err_cnt,
4174 dm_info->ht_err_cnt, dm_info->vht_err_cnt);