Lines Matching full:dev
15 struct mt7996_dev *dev; in mt7996_poll_tx() local
17 dev = container_of(napi, struct mt7996_dev, mt76.tx_napi); in mt7996_poll_tx()
19 mt76_connac_tx_cleanup(&dev->mt76); in mt7996_poll_tx()
21 mt7996_irq_enable(dev, MT_INT_TX_DONE_MCU); in mt7996_poll_tx()
26 static void mt7996_dma_config(struct mt7996_dev *dev) in mt7996_dma_config() argument
30 dev->q_wfdma_mask |= (1 << (q)); \ in mt7996_dma_config()
31 dev->q_int_mask[(q)] = int; \ in mt7996_dma_config()
32 dev->q_id[(q)] = id; \ in mt7996_dma_config()
62 static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs) in __mt7996_dma_prefetch() argument
66 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x2)); in __mt7996_dma_prefetch()
67 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x20, 0x2)); in __mt7996_dma_prefetch()
68 mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x40, 0x4)); in __mt7996_dma_prefetch()
69 mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x80, 0x4)); in __mt7996_dma_prefetch()
70 mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0xc0, 0x2)); in __mt7996_dma_prefetch()
71 mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0xe0, 0x4)); in __mt7996_dma_prefetch()
72 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x120, 0x2)); in __mt7996_dma_prefetch()
73 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x140, 0x2)); in __mt7996_dma_prefetch()
74 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x160, 0x2)); in __mt7996_dma_prefetch()
75 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x180, 0x2)); in __mt7996_dma_prefetch()
76 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x1a0, 0x10)); in __mt7996_dma_prefetch()
77 mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x2a0, 0x10)); in __mt7996_dma_prefetch()
79 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + ofs, WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE); in __mt7996_dma_prefetch()
82 void mt7996_dma_prefetch(struct mt7996_dev *dev) in mt7996_dma_prefetch() argument
84 __mt7996_dma_prefetch(dev, 0); in mt7996_dma_prefetch()
85 if (dev->hif2) in mt7996_dma_prefetch()
86 __mt7996_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0)); in mt7996_dma_prefetch()
89 static void mt7996_dma_disable(struct mt7996_dev *dev, bool reset) in mt7996_dma_disable() argument
93 if (dev->hif2) in mt7996_dma_disable()
97 mt76_clear(dev, MT_WFDMA0_RST, in mt7996_dma_disable()
101 mt76_set(dev, MT_WFDMA0_RST, in mt7996_dma_disable()
105 if (dev->hif2) { in mt7996_dma_disable()
106 mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs, in mt7996_dma_disable()
110 mt76_set(dev, MT_WFDMA0_RST + hif1_ofs, in mt7996_dma_disable()
117 mt76_clear(dev, MT_WFDMA0_GLO_CFG, in mt7996_dma_disable()
124 if (dev->hif2) { in mt7996_dma_disable()
125 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, in mt7996_dma_disable()
134 void mt7996_dma_start(struct mt7996_dev *dev, bool reset) in mt7996_dma_start() argument
139 if (dev->hif2) in mt7996_dma_start()
144 mt76_set(dev, MT_WFDMA0_GLO_CFG, in mt7996_dma_start()
150 if (dev->hif2) in mt7996_dma_start()
151 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, in mt7996_dma_start()
165 if (!dev->mphy.band_idx) in mt7996_dma_start()
168 if (dev->dbdc_support) in mt7996_dma_start()
171 if (dev->tbtc_support) in mt7996_dma_start()
175 mt7996_irq_enable(dev, irq_mask); in mt7996_dma_start()
176 mt7996_irq_disable(dev, 0); in mt7996_dma_start()
179 static void mt7996_dma_enable(struct mt7996_dev *dev, bool reset) in mt7996_dma_enable() argument
183 if (dev->hif2) in mt7996_dma_enable()
187 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0); in mt7996_dma_enable()
188 if (dev->hif2) in mt7996_dma_enable()
189 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0); in mt7996_dma_enable()
192 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0); in mt7996_dma_enable()
193 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1, 0); in mt7996_dma_enable()
194 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2, 0); in mt7996_dma_enable()
196 if (dev->hif2) { in mt7996_dma_enable()
197 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0); in mt7996_dma_enable()
198 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 + hif1_ofs, 0); in mt7996_dma_enable()
199 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 + hif1_ofs, 0); in mt7996_dma_enable()
203 mt7996_dma_prefetch(dev); in mt7996_dma_enable()
206 mt76_set(dev, MT_WFDMA0_BUSY_ENA, in mt7996_dma_enable()
211 if (dev->hif2) in mt7996_dma_enable()
212 mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs, in mt7996_dma_enable()
217 mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC, in mt7996_dma_enable()
221 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0, in mt7996_dma_enable()
226 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1, in mt7996_dma_enable()
229 if (dev->hif2) { in mt7996_dma_enable()
231 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs, in mt7996_dma_enable()
236 mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + hif1_ofs, in mt7996_dma_enable()
239 mt76_set(dev, MT_WFDMA_HOST_CONFIG, in mt7996_dma_enable()
243 if (dev->hif2) { in mt7996_dma_enable()
247 mt76_set(dev, MT_WFDMA0_RX_INT_PCIE_SEL, in mt7996_dma_enable()
253 mt7996_dma_start(dev, reset); in mt7996_dma_enable()
256 int mt7996_dma_init(struct mt7996_dev *dev) in mt7996_dma_init() argument
261 mt7996_dma_config(dev); in mt7996_dma_init()
263 mt76_dma_attach(&dev->mt76); in mt7996_dma_init()
265 if (dev->hif2) in mt7996_dma_init()
268 mt7996_dma_disable(dev, true); in mt7996_dma_init()
271 ret = mt76_connac_init_tx_queues(dev->phy.mt76, in mt7996_dma_init()
272 MT_TXQ_ID(dev->mphy.band_idx), in mt7996_dma_init()
279 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, in mt7996_dma_init()
287 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA, in mt7996_dma_init()
295 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, in mt7996_dma_init()
303 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], in mt7996_dma_init()
312 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], in mt7996_dma_init()
321 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], in mt7996_dma_init()
330 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA], in mt7996_dma_init()
338 if (dev->tbtc_support || dev->mphy.band_idx == MT_BAND2) { in mt7996_dma_init()
340 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2], in mt7996_dma_init()
351 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2_WA], in mt7996_dma_init()
360 ret = mt76_init_queues(dev, mt76_dma_rx_poll); in mt7996_dma_init()
364 netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, in mt7996_dma_init()
366 napi_enable(&dev->mt76.tx_napi); in mt7996_dma_init()
368 mt7996_dma_enable(dev, false); in mt7996_dma_init()
373 void mt7996_dma_reset(struct mt7996_dev *dev, bool force) in mt7996_dma_reset() argument
375 struct mt76_phy *phy2 = dev->mt76.phys[MT_BAND1]; in mt7996_dma_reset()
376 struct mt76_phy *phy3 = dev->mt76.phys[MT_BAND2]; in mt7996_dma_reset()
380 mt76_clear(dev, MT_WFDMA0_GLO_CFG, in mt7996_dma_reset()
384 if (dev->hif2) in mt7996_dma_reset()
385 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs, in mt7996_dma_reset()
392 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); in mt7996_dma_reset()
394 mt76_queue_tx_cleanup(dev, phy2->q_tx[i], true); in mt7996_dma_reset()
396 mt76_queue_tx_cleanup(dev, phy3->q_tx[i], true); in mt7996_dma_reset()
400 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true); in mt7996_dma_reset()
402 mt76_for_each_q_rx(&dev->mt76, i) in mt7996_dma_reset()
403 mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]); in mt7996_dma_reset()
405 mt76_tx_status_check(&dev->mt76, true); in mt7996_dma_reset()
409 mt7996_wfsys_reset(dev); in mt7996_dma_reset()
411 mt7996_dma_disable(dev, force); in mt7996_dma_reset()
415 mt76_queue_reset(dev, dev->mphy.q_tx[i]); in mt7996_dma_reset()
417 mt76_queue_reset(dev, phy2->q_tx[i]); in mt7996_dma_reset()
419 mt76_queue_reset(dev, phy3->q_tx[i]); in mt7996_dma_reset()
423 mt76_queue_reset(dev, dev->mt76.q_mcu[i]); in mt7996_dma_reset()
425 mt76_for_each_q_rx(&dev->mt76, i) { in mt7996_dma_reset()
426 mt76_queue_reset(dev, &dev->mt76.q_rx[i]); in mt7996_dma_reset()
429 mt76_tx_status_check(&dev->mt76, true); in mt7996_dma_reset()
431 mt76_for_each_q_rx(&dev->mt76, i) in mt7996_dma_reset()
432 mt76_queue_rx_reset(dev, i); in mt7996_dma_reset()
434 mt7996_dma_enable(dev, !force); in mt7996_dma_reset()
437 void mt7996_dma_cleanup(struct mt7996_dev *dev) in mt7996_dma_cleanup() argument
439 mt7996_dma_disable(dev, true); in mt7996_dma_cleanup()
441 mt76_dma_cleanup(&dev->mt76); in mt7996_dma_cleanup()