261 	al_reg_write32(regs->axi.parity.en_axi,  in al_pcie_port_axi_parity_int_config()
265 		al_reg_write32_masked(regs->axi.ctrl.global,  in al_pcie_port_axi_parity_int_config()
277 		al_reg_write32_masked(regs->axi.ctrl.global,  in al_pcie_port_axi_parity_int_config()
290 	al_reg_write32_masked(&regs->axi.int_grp_a->mask,  in al_pcie_port_axi_parity_int_config()
330 		regs->axi.ordering.pos_cntl,  in al_pcie_port_relaxed_pcie_ordering_config()
366 		dev_id = al_reg_read32(&regs->axi.device_id.device_rev_id) &  in al_pcie_rev_id_get()
603 	al_reg_write32(regs->axi.conf.zero_lane0, reg);  in al_pcie_port_gen3_params_config()
604 	al_reg_write32(regs->axi.conf.zero_lane1, reg);  in al_pcie_port_gen3_params_config()
605 	al_reg_write32(regs->axi.conf.zero_lane2, reg);  in al_pcie_port_gen3_params_config()
606 	al_reg_write32(regs->axi.conf.zero_lane3, reg);  in al_pcie_port_gen3_params_config()
608 		al_reg_write32(regs->axi.conf.zero_lane4, reg);  in al_pcie_port_gen3_params_config()
609 		al_reg_write32(regs->axi.conf.zero_lane5, reg);  in al_pcie_port_gen3_params_config()
610 		al_reg_write32(regs->axi.conf.zero_lane6, reg);  in al_pcie_port_gen3_params_config()
611 		al_reg_write32(regs->axi.conf.zero_lane7, reg);  in al_pcie_port_gen3_params_config()
1004 		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;  in al_pcie_port_handle_init()
1005 		pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;  in al_pcie_port_handle_init()
1006 		pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;  in al_pcie_port_handle_init()
1007 		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;  in al_pcie_port_handle_init()
1008 		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;  in al_pcie_port_handle_init()
1009 		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;  in al_pcie_port_handle_init()
1010 		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;  in al_pcie_port_handle_init()
1011 		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;  in al_pcie_port_handle_init()
1012 		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;  in al_pcie_port_handle_init()
1013 		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;  in al_pcie_port_handle_init()
1014 		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;  in al_pcie_port_handle_init()
1015 		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;  in al_pcie_port_handle_init()
1016 		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;  in al_pcie_port_handle_init()
1017 		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;  in al_pcie_port_handle_init()
1018 		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;  in al_pcie_port_handle_init()
1019 		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;  in al_pcie_port_handle_init()
1020 		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;  in al_pcie_port_handle_init()
1021 		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;  in al_pcie_port_handle_init()
1022 		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;  in al_pcie_port_handle_init()
1023 		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;  in al_pcie_port_handle_init()
1024 		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;  in al_pcie_port_handle_init()
1025 		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;  in al_pcie_port_handle_init()
1026 		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;  in al_pcie_port_handle_init()
1027 …pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_se…  in al_pcie_port_handle_init()
1028 		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;  in al_pcie_port_handle_init()
1029 		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;  in al_pcie_port_handle_init()
1067 		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;  in al_pcie_port_handle_init()
1068 		pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;  in al_pcie_port_handle_init()
1069 		pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;  in al_pcie_port_handle_init()
1070 		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;  in al_pcie_port_handle_init()
1071 		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;  in al_pcie_port_handle_init()
1072 		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;  in al_pcie_port_handle_init()
1073 		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;  in al_pcie_port_handle_init()
1074 		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;  in al_pcie_port_handle_init()
1075 		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;  in al_pcie_port_handle_init()
1076 		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;  in al_pcie_port_handle_init()
1077 		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;  in al_pcie_port_handle_init()
1078 		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;  in al_pcie_port_handle_init()
1079 		pcie_port->regs->axi.ob_ctrl.tgtid_reg_ovrd = &regs->axi.ob_ctrl.tgtid_reg_ovrd;  in al_pcie_port_handle_init()
1080 		pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_sel = &regs->axi.ob_ctrl.addr_high_reg_ovrd_sel;  in al_pcie_port_handle_init()
1081 …pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_value = &regs->axi.ob_ctrl.addr_high_reg_ovrd_valu…  in al_pcie_port_handle_init()
1082 		pcie_port->regs->axi.ob_ctrl.addr_size_replace = &regs->axi.ob_ctrl.addr_size_replace;  in al_pcie_port_handle_init()
1083 		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;  in al_pcie_port_handle_init()
1084 		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;  in al_pcie_port_handle_init()
1085 		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;  in al_pcie_port_handle_init()
1086 		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;  in al_pcie_port_handle_init()
1087 		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;  in al_pcie_port_handle_init()
1088 		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;  in al_pcie_port_handle_init()
1089 		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;  in al_pcie_port_handle_init()
1090 		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;  in al_pcie_port_handle_init()
1091 		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;  in al_pcie_port_handle_init()
1092 		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;  in al_pcie_port_handle_init()
1093 		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;  in al_pcie_port_handle_init()
1094 …pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_se…  in al_pcie_port_handle_init()
1095 		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;  in al_pcie_port_handle_init()
1096 		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;  in al_pcie_port_handle_init()
1141 		pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;  in al_pcie_port_handle_init()
1142 		pcie_port->regs->axi.ctrl.master_rctl = &regs->axi.ctrl.master_rctl;  in al_pcie_port_handle_init()
1143 		pcie_port->regs->axi.ctrl.master_ctl = &regs->axi.ctrl.master_ctl;  in al_pcie_port_handle_init()
1144 		pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;  in al_pcie_port_handle_init()
1145 		pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;  in al_pcie_port_handle_init()
1146 		pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;  in al_pcie_port_handle_init()
1147 		pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;  in al_pcie_port_handle_init()
1148 		pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;  in al_pcie_port_handle_init()
1149 		pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;  in al_pcie_port_handle_init()
1150 		pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;  in al_pcie_port_handle_init()
1151 		pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;  in al_pcie_port_handle_init()
1152 		pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;  in al_pcie_port_handle_init()
1153 		pcie_port->regs->axi.ob_ctrl.io_addr_mask_h = &regs->axi.ob_ctrl.io_addr_mask_h;  in al_pcie_port_handle_init()
1154 		pcie_port->regs->axi.ob_ctrl.ar_msg_addr_mask_h = &regs->axi.ob_ctrl.ar_msg_addr_mask_h;  in al_pcie_port_handle_init()
1155 		pcie_port->regs->axi.ob_ctrl.aw_msg_addr_mask_h = &regs->axi.ob_ctrl.aw_msg_addr_mask_h;  in al_pcie_port_handle_init()
1156 		pcie_port->regs->axi.ob_ctrl.tgtid_reg_ovrd = &regs->axi.ob_ctrl.tgtid_reg_ovrd;  in al_pcie_port_handle_init()
1157 		pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_sel = &regs->axi.ob_ctrl.addr_high_reg_ovrd_sel;  in al_pcie_port_handle_init()
1158 …pcie_port->regs->axi.ob_ctrl.addr_high_reg_ovrd_value = &regs->axi.ob_ctrl.addr_high_reg_ovrd_valu…  in al_pcie_port_handle_init()
1159 		pcie_port->regs->axi.ob_ctrl.addr_size_replace = &regs->axi.ob_ctrl.addr_size_replace;  in al_pcie_port_handle_init()
1160 		pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;  in al_pcie_port_handle_init()
1161 		pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;  in al_pcie_port_handle_init()
1162 		pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;  in al_pcie_port_handle_init()
1163 		pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;  in al_pcie_port_handle_init()
1164 		pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;  in al_pcie_port_handle_init()
1165 		pcie_port->regs->axi.conf.zero_lane4 = &regs->axi.conf.zero_lane4;  in al_pcie_port_handle_init()
1166 		pcie_port->regs->axi.conf.zero_lane5 = &regs->axi.conf.zero_lane5;  in al_pcie_port_handle_init()
1167 		pcie_port->regs->axi.conf.zero_lane6 = &regs->axi.conf.zero_lane6;  in al_pcie_port_handle_init()
1168 		pcie_port->regs->axi.conf.zero_lane7 = &regs->axi.conf.zero_lane7;  in al_pcie_port_handle_init()
1169 		pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;  in al_pcie_port_handle_init()
1170 		pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;  in al_pcie_port_handle_init()
1171 		pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;  in al_pcie_port_handle_init()
1172 		pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;  in al_pcie_port_handle_init()
1173 		pcie_port->regs->axi.status.lane[4] = &regs->axi.status.lane4;  in al_pcie_port_handle_init()
1174 		pcie_port->regs->axi.status.lane[5] = &regs->axi.status.lane5;  in al_pcie_port_handle_init()
1175 		pcie_port->regs->axi.status.lane[6] = &regs->axi.status.lane6;  in al_pcie_port_handle_init()
1176 		pcie_port->regs->axi.status.lane[7] = &regs->axi.status.lane7;  in al_pcie_port_handle_init()
1177 		pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;  in al_pcie_port_handle_init()
1178 		pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;  in al_pcie_port_handle_init()
1179 …pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_se…  in al_pcie_port_handle_init()
1180 		pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;  in al_pcie_port_handle_init()
1181 		pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;  in al_pcie_port_handle_init()
1182 		pcie_port->regs->axi.axi_attr_ovrd.write_msg_ctrl_0 = &regs->axi.axi_attr_ovrd.write_msg_ctrl_0;  in al_pcie_port_handle_init()
1183 		pcie_port->regs->axi.axi_attr_ovrd.write_msg_ctrl_1 = &regs->axi.axi_attr_ovrd.write_msg_ctrl_1;  in al_pcie_port_handle_init()
1184 		pcie_port->regs->axi.axi_attr_ovrd.pf_sel = &regs->axi.axi_attr_ovrd.pf_sel;  in al_pcie_port_handle_init()
1187 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_0 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_0;  in al_pcie_port_handle_init()
1188 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_1 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_1;  in al_pcie_port_handle_init()
1189 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_2 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_2;  in al_pcie_port_handle_init()
1190 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_3 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_3;  in al_pcie_port_handle_init()
1191 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_4 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_4;  in al_pcie_port_handle_init()
1192 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_5 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_5;  in al_pcie_port_handle_init()
1193 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_6 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_6;  in al_pcie_port_handle_init()
1194 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_7 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_7;  in al_pcie_port_handle_init()
1195 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_8 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_8;  in al_pcie_port_handle_init()
1196 …	pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_9 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_9;  in al_pcie_port_handle_init()
1199 		pcie_port->regs->axi.msg_attr_axuser_table.entry_vec = &regs->axi.msg_attr_axuser_table.entry_vec;  in al_pcie_port_handle_init()
1331 	reg = al_reg_read32(regs->axi.pcie_global.conf);  in al_pcie_port_operating_mode_config()
1343 			al_reg_write32_masked(regs->axi.axi_attr_ovrd.pf_sel,  in al_pcie_port_operating_mode_config()
1373 	al_reg_write32(regs->axi.pcie_global.conf, reg);  in al_pcie_port_operating_mode_config()
1393 	al_reg_write32_masked(regs->axi.pcie_global.conf,  in al_pcie_port_max_lanes_set()
1475 			regs->axi.init_fc.cfg,  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1493 			regs->axi.init_fc.cfg,  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1506 		regs->axi.pre_configuration.pcie_core_setup,  in al_pcie_port_ib_hcrd_os_ob_reads_config()
1529 	reg = al_reg_read32(regs->axi.pcie_global.conf);  in al_pcie_operating_mode_get()
1547 /* PCIe AXI quality of service configuration */
1560 		regs->axi.ctrl.master_arctl,  in al_pcie_axi_qos_config()
1564 		regs->axi.ctrl.master_awctl,  in al_pcie_axi_qos_config()
1599 			regs->axi.ordering.pos_cntl,  in al_pcie_port_enable()
1649 	al_reg_write32_masked(regs->axi.pcie_global.conf,  in al_pcie_port_memory_shutdown_set()
1702 		uint32_t global_conf = al_reg_read32(regs->axi.pcie_global.conf);  in al_pcie_port_config()
1820 		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_target_bus,  in al_pcie_port_config()
1823 		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_control,  in al_pcie_port_config()
1861 		al_reg_write32_masked(regs->axi.ob_ctrl.cfg_target_bus,  in al_pcie_port_config()
2051 	reg_ptr = regs->axi.status.lane[lane];  in al_pcie_lane_status_get()
2213 		al_reg_write32_masked(regs->axi.ctrl.master_arctl,  in al_pcie_port_snoop_config()
2217 		al_reg_write32_masked(regs->axi.ctrl.master_awctl,  in al_pcie_port_snoop_config()
2221 		al_reg_write32_masked(regs->axi.ctrl.master_arctl,  in al_pcie_port_snoop_config()
2225 		al_reg_write32_masked(regs->axi.ctrl.master_awctl,  in al_pcie_port_snoop_config()
2295 	reg = al_reg_read32(regs->axi.ob_ctrl.cfg_target_bus);  in al_pcie_target_bus_set()
2302 	al_reg_write32(regs->axi.ob_ctrl.cfg_target_bus, reg);  in al_pcie_target_bus_set()
2319 	reg = al_reg_read32(regs->axi.ob_ctrl.cfg_target_bus);  in al_pcie_target_bus_get()
2340 		regs->axi.ob_ctrl.cfg_control,  in al_pcie_secondary_bus_set()
2356 		regs->axi.ob_ctrl.cfg_control,  in al_pcie_subordinary_bus_set()
2407 	 * With AHB/AXI Bridge Module When the bridge slave interface clock  in al_pcie_atu_region_set()
2410 	 * are in progress on the AHB/AXI bridge slave interface. The iATU  in al_pcie_atu_region_set()
2412 	 * used in the AHB/AXI bridge slave interface clock domain. There is no  in al_pcie_atu_region_set()
2413 	 * synchronization logic between these registers and the AHB/AXI bridge  in al_pcie_atu_region_set()
2607 	al_reg_write32(regs->axi.ob_ctrl.io_start_h,  in al_pcie_axi_io_config()
2610 	al_reg_write32(regs->axi.ob_ctrl.io_start_l,  in al_pcie_axi_io_config()
2613 	al_reg_write32(regs->axi.ob_ctrl.io_limit_h,  in al_pcie_axi_io_config()
2616 	al_reg_write32(regs->axi.ob_ctrl.io_limit_l,  in al_pcie_axi_io_config()
2619 	al_reg_write32_masked(regs->axi.ctrl.slv_ctl,  in al_pcie_axi_io_config()