Lines Matching +full:irqs +full:- +full:map +full:- +full:range
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
78 #define ATU_OB_REGION_0_SIZE (( ATU_OB_REGIONS - 1) * ATU_OB_REGION_SIZE)
179 #define APB_WR4(_sc, _r, _v) bus_write_4((_sc)->apb_mem_res, (_r), (_v))
180 #define APB_RD4(_sc, _r) bus_read_4((_sc)->apb_mem_res, (_r))
240 {"rockchip,rk3399-pcie", 1},
258 val = bus_read_4(sc->apb_mem_res, base + reg);
261 val = bus_read_2(sc->apb_mem_res, base + reg);
264 val = bus_read_1(sc->apb_mem_res, base + reg);
286 bus_write_4(sc->apb_mem_res, base + reg, val);
289 val2 = bus_read_4(sc->apb_mem_res, base + (reg & ~3));
292 bus_write_4(sc->apb_mem_res, base + (reg & ~3), val2);
295 val2 = bus_read_4(sc->apb_mem_res, base + (reg & ~3));
298 bus_write_4(sc->apb_mem_res, base + (reg & ~3), val2);
309 if (bus < sc->bus_start || bus > sc->bus_end || slot > PCI_SLOTMAX ||
313 if (bus == sc->root_bus) {
320 /* link is needed for accessing non-root busses */
326 if (bus == sc->sub_bus && slot != 0 )
351 APB_WR4(sc, PCIE_CORE_OB_DESC1(idx), sc->root_bus);
366 * range into it. Remaining bits of bus number should be taken from
369 APB_WR4(sc, PCIE_CORE_OB_ADDR0(idx), 25 - 1);
372 APB_WR4(sc, PCIE_CORE_OB_DESC1(idx), sc->root_bus);
407 if (sc->io_range.size != 0) {
408 device_printf(sc->dev,
409 "Duplicated IO range found in DT\n");
412 sc->io_range = ranges[i];
417 if (sc->pref_mem_range.size != 0) {
418 device_printf(sc->dev,
419 "Duplicated memory range found "
423 sc->pref_mem_range = ranges[i];
425 if (sc->mem_range.size != 0) {
426 device_printf(sc->dev,
427 "Duplicated memory range found "
431 sc->mem_range = ranges[i];
435 if (sc->mem_range.size == 0) {
436 device_printf(sc->dev,
437 " At least memory range should be defined in DT.\n");
443 /*-----------------------------------------------------------------------------
462 if (bus == sc->root_bus)
467 type = bus == sc->sub_bus ? ATU_TYPE_CFG0: ATU_TYPE_CFG1;
470 ret = -1;
473 ret = bus_peek_1(sc->axi_mem_res, addr, &d8);
477 ret = bus_peek_2(sc->axi_mem_res, addr, &d16);
481 ret = bus_peek_4(sc->axi_mem_res, addr, &d32);
503 if (bus == sc->root_bus)
508 type = bus == sc->sub_bus ? ATU_TYPE_CFG0: ATU_TYPE_CFG1;
513 bus_poke_1(sc->axi_mem_res, addr, (uint8_t)val);
516 bus_poke_2(sc->axi_mem_res, addr, (uint16_t)val);
519 bus_poke_4(sc->axi_mem_res, addr, val);
529 int maxcount, int *irqs)
539 rv = intr_alloc_msi(pci, child, msi_parent, count, maxcount,irqs);
544 rk_pcie_release_msi(device_t pci, device_t child, int count, int *irqs)
553 rv = intr_release_msi(pci, child, msi_parent, count, irqs);
633 irq = intr_map_clone_irq(rman_get_start(sc->legacy_irq_res));
640 /*-----------------------------------------------------------------------------
651 rv = regulator_get_by_ofw_property(sc->dev, 0,
652 "vpcie12v-supply", &sc->supply_12v);
654 device_printf(sc->dev,"Cannot get 'vpcie12' regulator\n");
657 rv = regulator_get_by_ofw_property(sc->dev, 0,
658 "vpcie3v3-supply", &sc->supply_3v3);
660 device_printf(sc->dev,"Cannot get 'vpcie3v3' regulator\n");
663 rv = regulator_get_by_ofw_property(sc->dev, 0,
664 "vpcie1v8-supply", &sc->supply_1v8);
666 device_printf(sc->dev,"Cannot get 'vpcie1v8' regulator\n");
669 rv = regulator_get_by_ofw_property(sc->dev, 0,
670 "vpcie0v9-supply", &sc->supply_0v9);
672 device_printf(sc->dev,"Cannot get 'vpcie0v9' regulator\n");
677 rv = hwreset_get_by_ofw_name(sc->dev, 0, "core", &sc->hwreset_core);
679 device_printf(sc->dev, "Cannot get 'core' reset\n");
682 rv = hwreset_get_by_ofw_name(sc->dev, 0, "mgmt", &sc->hwreset_mgmt);
684 device_printf(sc->dev, "Cannot get 'mgmt' reset\n");
687 rv = hwreset_get_by_ofw_name(sc->dev, 0, "mgmt-sticky",
688 &sc->hwreset_mgmt_sticky);
690 device_printf(sc->dev, "Cannot get 'mgmt-sticky' reset\n");
693 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pipe", &sc->hwreset_pipe);
695 device_printf(sc->dev, "Cannot get 'pipe' reset\n");
698 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pm", &sc->hwreset_pm);
700 device_printf(sc->dev, "Cannot get 'pm' reset\n");
703 rv = hwreset_get_by_ofw_name(sc->dev, 0, "aclk", &sc->hwreset_aclk);
705 device_printf(sc->dev, "Cannot get 'aclk' reset\n");
708 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pclk", &sc->hwreset_pclk);
710 device_printf(sc->dev, "Cannot get 'pclk' reset\n");
715 rv = clk_get_by_ofw_name(sc->dev, 0, "aclk", &sc->clk_aclk);
717 device_printf(sc->dev, "Cannot get 'aclk' clock\n");
720 rv = clk_get_by_ofw_name(sc->dev, 0, "aclk-perf", &sc->clk_aclk_perf);
722 device_printf(sc->dev, "Cannot get 'aclk-perf' clock\n");
725 rv = clk_get_by_ofw_name(sc->dev, 0, "hclk", &sc->clk_hclk);
727 device_printf(sc->dev, "Cannot get 'hclk' clock\n");
730 rv = clk_get_by_ofw_name(sc->dev, 0, "pm", &sc->clk_pm);
732 device_printf(sc->dev, "Cannot get 'pm' clock\n");
738 sprintf (buf, "pcie-phy-%d", i);
739 rv = phy_get_by_ofw_name(sc->dev, 0, buf, sc->phys + i);
741 device_printf(sc->dev, "Cannot get '%s' phy\n", buf);
747 rv = gpio_pin_get_by_ofw_property(sc->dev, sc->node, "ep-gpios",
748 &sc->gpio_ep);
750 device_printf(sc->dev, "Cannot get 'ep-gpios' gpio\n");
764 rv = hwreset_assert(sc->hwreset_pclk);
766 device_printf(sc->dev, "Cannot assert 'pclk' reset\n");
769 rv = hwreset_assert(sc->hwreset_aclk);
771 device_printf(sc->dev, "Cannot assert 'aclk' reset\n");
774 rv = hwreset_assert(sc->hwreset_pm);
776 device_printf(sc->dev, "Cannot assert 'pm' reset\n");
779 rv = hwreset_assert(sc->hwreset_pipe);
781 device_printf(sc->dev, "Cannot assert 'pipe' reset\n");
784 rv = hwreset_assert(sc->hwreset_mgmt_sticky);
786 device_printf(sc->dev, "Cannot assert 'mgmt_sticky' reset\n");
789 rv = hwreset_assert(sc->hwreset_mgmt);
791 device_printf(sc->dev, "Cannot assert 'hmgmt' reset\n");
794 rv = hwreset_assert(sc->hwreset_core);
796 device_printf(sc->dev, "Cannot assert 'hcore' reset\n");
802 rv = clk_enable(sc->clk_aclk);
804 device_printf(sc->dev, "Cannot enable 'aclk' clock\n");
807 rv = clk_enable(sc->clk_aclk_perf);
809 device_printf(sc->dev, "Cannot enable 'aclk_perf' clock\n");
812 rv = clk_enable(sc->clk_hclk);
814 device_printf(sc->dev, "Cannot enable 'hclk' clock\n");
817 rv = clk_enable(sc->clk_pm);
819 device_printf(sc->dev, "Cannot enable 'pm' clock\n");
824 if (sc->supply_12v != NULL) {
825 rv = regulator_enable(sc->supply_12v);
827 device_printf(sc->dev,
832 if (sc->supply_3v3 != NULL) {
833 rv = regulator_enable(sc->supply_3v3);
835 device_printf(sc->dev,
840 if (sc->supply_1v8 != NULL) {
841 rv = regulator_enable(sc->supply_1v8);
843 device_printf(sc->dev,
848 if (sc->supply_0v9 != NULL) {
849 rv = regulator_enable(sc->supply_0v9);
851 device_printf(sc->dev,
859 rv = hwreset_deassert(sc->hwreset_pm);
861 device_printf(sc->dev, "Cannot deassert 'pm' reset\n");
864 rv = hwreset_deassert(sc->hwreset_aclk);
866 device_printf(sc->dev, "Cannot deassert 'aclk' reset\n");
869 rv = hwreset_deassert(sc->hwreset_pclk);
871 device_printf(sc->dev, "Cannot deassert 'pclk' reset\n");
877 (sc->link_is_gen2 ? STRAP_CONF_GEN_2: 0);
879 val |= STRAP_CONF_LANES(~0) << 16 | STRAP_CONF_LANES(sc->num_lanes);
885 rv = phy_enable(sc->phys[i]);
887 device_printf(sc->dev, "Cannot enable phy %d\n", i);
892 /* Deassert rest of resets - order is important ! */
893 rv = hwreset_deassert(sc->hwreset_mgmt_sticky);
895 device_printf(sc->dev, "Cannot deassert 'mgmt_sticky' reset\n");
898 rv = hwreset_deassert(sc->hwreset_core);
900 device_printf(sc->dev, "Cannot deassert 'core' reset\n");
903 rv = hwreset_deassert(sc->hwreset_mgmt);
905 device_printf(sc->dev, "Cannot deassert 'mgmt' reset\n");
908 rv = hwreset_deassert(sc->hwreset_pipe);
910 device_printf(sc->dev, "Cannot deassert 'pipe' reset\n");
923 if (sc->gpio_ep != NULL) {
924 rv = gpio_pin_set_active(sc->gpio_ep, 0);
926 device_printf(sc->dev,
927 "Cannot clear 'gpio-ep' gpio\n");
954 if (sc->gpio_ep != NULL) {
955 rv = gpio_pin_set_active(sc->gpio_ep, 1);
957 device_printf(sc->dev, "Cannot set 'gpio-ep' gpio\n");
963 for (i = 500; i > 0; i--) {
970 device_printf(sc->dev,
975 if (sc->link_is_gen2) {
981 for (i = 500; i > 0; i--) {
989 device_printf(sc->dev, "Gen2 link training "
996 device_printf(sc->dev, "Link width: %d\n", 1 << val);
1007 pcib_bridge_init(sc->dev);
1013 PRIV_CFG_WR1(sc, PCIR_PRIBUS_1, sc->root_bus);
1014 PRIV_CFG_WR1(sc, PCIR_SECBUS_1, sc->sub_bus);
1015 PRIV_CFG_WR1(sc, PCIR_SUBBUS_1, sc->bus_end);
1025 if (sc->no_l0s) {
1039 * map whole address range in 1:1 mappings
1041 rk_pcie_map_in_atu(sc, 2, 64 - 1, 0);
1044 /* - region 0 (32 MB) is used for config access */
1046 rk_pcie_map_out_atu(sc, region++, ATU_TYPE_CFG0, 25 - 1, 0);
1048 /* - then map memory (by using 1MB regions */
1049 for (i = 0; i < sc->mem_range.size / ATU_OB_REGION_SIZE; i++) {
1051 ATU_OB_REGION_SHIFT - 1,
1052 sc->mem_range.pci + ATU_OB_REGION_SIZE * i);
1055 /* - IO space is next, one region typically*/
1056 for (i = 0; i < sc->io_range.size / ATU_OB_REGION_SIZE; i++) {
1058 ATU_OB_REGION_SHIFT - 1,
1059 sc->io_range.pci + ATU_OB_REGION_SIZE * i);
1078 device_printf(sc->dev, "'sys' interrupt received: 0x%04X\n",
1098 device_printf(sc->dev, "'client' interrupt received: 0x%04X\n", irq);
1124 return (sc->dmat);
1134 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1145 struct resource_map map;
1151 sc->dev = dev;
1152 sc->node = ofw_bus_get_node(dev);
1154 mtx_init(&sc->mtx, "rk_pcie_mtx", NULL, MTX_DEF);
1157 sc->bus_start = 0;
1158 sc->bus_end = 0x1F;
1159 sc->root_bus = sc->bus_start;
1160 sc->sub_bus = 1;
1167 sc->coherent = OF_hasprop(sc->node, "dma-coherent");
1168 sc->no_l0s = OF_hasprop(sc->node, "aspm-no-l0s");
1169 rv = OF_getencprop(sc->node, "num-lanes", &sc->num_lanes,
1170 sizeof(sc->num_lanes));
1171 if (rv != sizeof(sc->num_lanes))
1172 sc->num_lanes = 1;
1173 if (sc->num_lanes != 1 && sc->num_lanes != 2 && sc->num_lanes != 4) {
1175 "invalid number of lanes: %d\n",sc->num_lanes);
1176 sc->num_lanes = 0;
1181 rv = OF_getencprop(sc->node, "max-link-speed", &max_speed,
1184 sc->link_is_gen2 = true;
1186 sc->link_is_gen2 = false;
1188 rv = ofw_bus_find_string_index(sc->node, "reg-names", "axi-base", &rid);
1190 device_printf(dev, "Cannot get 'axi-base' memory\n");
1194 sc->axi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1196 if (sc->axi_mem_res == NULL) {
1197 device_printf(dev, "Cannot allocate 'axi-base' (rid: %d)\n",
1204 rv = bus_map_resource(dev, SYS_RES_MEMORY, sc->axi_mem_res, &req,
1205 &map);
1207 device_printf(dev, "Cannot map 'axi-base' (rid: %d)\n",
1211 rman_set_mapping(sc->axi_mem_res, &map);
1213 rv = ofw_bus_find_string_index(sc->node, "reg-names", "apb-base", &rid);
1215 device_printf(dev, "Cannot get 'apb-base' memory\n");
1219 sc->apb_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1221 if (sc->apb_mem_res == NULL) {
1222 device_printf(dev, "Cannot allocate 'apb-base' (rid: %d)\n",
1228 rv = ofw_bus_find_string_index(sc->node, "interrupt-names",
1235 sc->client_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1237 if (sc->client_irq_res == NULL) {
1243 rv = ofw_bus_find_string_index(sc->node, "interrupt-names",
1250 sc->legacy_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1252 if (sc->legacy_irq_res == NULL) {
1258 rv = ofw_bus_find_string_index(sc->node, "interrupt-names",
1265 sc->sys_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1267 if (sc->sys_irq_res == NULL) {
1274 device_printf(dev, "Bus is%s cache-coherent\n",
1275 sc->coherent ? "" : " not");
1284 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */
1286 &sc->dmat);
1294 rv = rk_pcie_decode_ranges(sc, sc->ofw_pci.sc_range,
1295 sc->ofw_pci.sc_nrange);
1306 rv = bus_setup_intr(dev, sc->client_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1307 rk_pcie_client_irq, NULL, sc, &sc->client_irq_cookie);
1314 rv = bus_setup_intr(dev, sc->legacy_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1315 rk_pcie_legacy_irq, NULL, sc, &sc->legacy_irq_cookie);
1322 rv = bus_setup_intr(dev, sc->sys_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1323 rk_pcie_sys_irq, NULL, sc, &sc->sys_irq_cookie);
1361 bus_teardown_intr(dev, sc->sys_irq_res, sc->sys_irq_cookie);
1362 bus_teardown_intr(dev, sc->legacy_irq_res, sc->legacy_irq_cookie);
1363 bus_teardown_intr(dev, sc->client_irq_res, sc->client_irq_cookie);
1366 bus_dma_tag_destroy(sc->dmat);
1367 bus_free_resource(dev, SYS_RES_IRQ, sc->sys_irq_res);
1368 bus_free_resource(dev, SYS_RES_IRQ, sc->legacy_irq_res);
1369 bus_free_resource(dev, SYS_RES_IRQ, sc->client_irq_res);
1370 bus_free_resource(dev, SYS_RES_MEMORY, sc->apb_mem_res);
1371 bus_free_resource(dev, SYS_RES_MEMORY, sc->axi_mem_res);
1373 gpio_pin_release(sc->gpio_ep);
1376 phy_release(sc->phys[i]);
1379 clk_release(sc->clk_aclk);
1380 clk_release(sc->clk_aclk_perf);
1381 clk_release(sc->clk_hclk);
1382 clk_release(sc->clk_pm);
1384 hwreset_release(sc->hwreset_core);
1385 hwreset_release(sc->hwreset_mgmt);
1386 hwreset_release(sc->hwreset_pipe);
1387 hwreset_release(sc->hwreset_pm);
1388 hwreset_release(sc->hwreset_aclk);
1389 hwreset_release(sc->hwreset_pclk);
1391 regulator_release(sc->supply_12v);
1392 regulator_release(sc->supply_3v3);
1393 regulator_release(sc->supply_1v8);
1394 regulator_release(sc->supply_0v9);