Lines Matching defs:div0
213 int div0, div1;
222 div0 = (io_pll_frequency + div1 * frequency / 2) /
224 if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX &&
225 ((io_pll_frequency / div0 / div1) + 500) / 1000 ==
241 (div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) |
314 int div0, div1;
344 div0 = (base_frequency + div1 * frequency / 2) /
346 if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX &&
347 ((base_frequency / div0 / div1) + 500) / 1000 ==
365 (div0 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT);
373 return (base_frequency / div0 / div1);
380 int div0, div1;
413 div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >>
418 if (div0 == 0)
419 div0 = 1;
424 frequency = (base_frequency / div0 / div1);