Lines Matching defs:unit
210 cgem_set_ref_clk(int unit, int frequency)
239 WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL,
257 zy7_pl_fclk_set_source(int unit, int source)
271 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
274 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
285 zy7_pl_fclk_get_source(int unit)
297 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
311 zy7_pl_fclk_set_freq(int unit, int frequency)
322 source = zy7_pl_fclk_get_source(unit);
361 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
366 WR4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit), reg);
377 zy7_pl_fclk_get_freq(int unit)
389 source = zy7_pl_fclk_get_source(unit);
410 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit));
433 zy7_pl_fclk_enable(int unit)
445 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
446 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 0);
457 zy7_pl_fclk_disable(int unit)
469 WR4(sc, ZY7_SLCR_FPGA_THR_CTRL(unit), 0);
470 WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1);
481 zy7_pl_fclk_enabled(int unit)
490 reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit));