Lines Matching +full:num +full:- +full:transfer +full:- +full:bits
1 /*-
93 for (i = 0; i < sc->sc_numcs; i++) {
103 while (j-- > 0)
108 device_printf(dev, "wordlen: %-2d clock: %d\n", wl, clk);
155 if (!ofw_bus_is_compatible(dev, "ti,omap4-mcspi"))
171 sc->sc_dev = dev;
181 if ((OF_getencprop(ofw_bus_get_node(dev), "ti,spi-num-cs",
182 &sc->sc_numcs, sizeof(sc->sc_numcs))) <= 0) {
183 sc->sc_numcs = 2;
187 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
189 if (!sc->sc_mem_res) {
194 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
195 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
198 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
200 if (!sc->sc_irq_res) {
201 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
207 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
208 NULL, ti_spi_intr, sc, &sc->sc_intrhand)) {
209 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
210 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
215 mtx_init(&sc->sc_mtx, "ti_spi", NULL, MTX_DEF);
222 if (--timeout == 0) {
250 for (i = 0; i < sc->sc_numcs; i++) {
252 * Default to SPI mode 0, CS active low, 8 bits word length and
257 (8 - 1) << MCSPI_CONF_WL_SHIFT);
258 /* Set initial clock - 500kHz. */
291 mtx_destroy(&sc->sc_mtx);
292 if (sc->sc_intrhand)
293 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
294 if (sc->sc_irq_res)
295 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
296 if (sc->sc_mem_res)
297 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
310 cmd = sc->sc_cmd;
311 bytes = min(sc->sc_len - sc->sc_written, sc->sc_fifolvl);
312 while (bytes-- > 0) {
313 data = (uint8_t *)cmd->tx_cmd;
314 written = sc->sc_written++;
315 if (written >= cmd->tx_cmd_sz) {
316 data = (uint8_t *)cmd->tx_data;
317 written -= cmd->tx_cmd_sz;
319 if (sc->sc_fifolvl == 1) {
322 while (--timeout > 0 && (TI_SPI_READ(sc,
323 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_TXS) == 0) {
327 return (-1);
329 TI_SPI_WRITE(sc, MCSPI_TX_CH(sc->sc_cs), data[written]);
343 cmd = sc->sc_cmd;
344 bytes = min(sc->sc_len - sc->sc_read, sc->sc_fifolvl);
345 while (bytes-- > 0) {
346 data = (uint8_t *)cmd->rx_cmd;
347 read = sc->sc_read++;
348 if (read >= cmd->rx_cmd_sz) {
349 data = (uint8_t *)cmd->rx_data;
350 read -= cmd->rx_cmd_sz;
352 if (sc->sc_fifolvl == 1) {
355 while (--timeout > 0 && (TI_SPI_READ(sc,
356 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_RXS) == 0) {
360 return (-1);
362 data[read] = TI_SPI_READ(sc, MCSPI_RX_CH(sc->sc_cs));
392 /* Check for end of transfer. */
393 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) {
394 sc->sc_flags |= TI_SPI_DONE;
395 wakeup(sc->sc_dev);
405 while (sc->sc_len - sc->sc_written > 0) {
406 if (ti_spi_fill_fifo(sc) == -1)
408 if (ti_spi_drain_fifo(sc) == -1)
437 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
439 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
449 if (cs > sc->sc_numcs) {
465 while (sc->sc_flags & TI_SPI_BUSY)
466 mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0);
469 sc->sc_flags = TI_SPI_BUSY;
472 sc->sc_cs = cs;
473 sc->sc_cmd = cmd;
474 sc->sc_read = 0;
475 sc->sc_written = 0;
476 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
477 sc->sc_fifolvl = ti_spi_gcd(sc->sc_len, TI_SPI_FIFOSZ);
478 if (sc->sc_fifolvl < 2 || sc->sc_len > 0xffff)
479 sc->sc_fifolvl = 1; /* FIFO disabled. */
481 sc->sc_fifolvl = 1;
484 ti_spi_set_clock(sc, sc->sc_cs, clockhz);
489 /* 8 bits word, d0 miso, d1 mosi, mode 0 and CS active low. */
490 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
496 reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */
497 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
506 /* Start the transfer. */
507 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs));
508 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg | MCSPI_CTRL_ENABLE);
511 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
512 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg |= MCSPI_CONF_FORCE);
515 if (sc->sc_fifolvl == 1)
519 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
521 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
530 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs));
532 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg);
535 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs));
537 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
540 sc->sc_flags = 0;