Lines Matching +full:atomic +full:- +full:threshold +full:- +full:us
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
117 /* { 3200000, 1, 113, 115, 7, 10}, - HS mode */
138 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
139 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
141 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
143 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
144 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
145 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
149 device_printf((_sc)->sc_dev, fmt, ##args)
155 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
164 * 16-bit value read from the register.
170 return (bus_read_2(sc->sc_mem_res, off));
174 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers
183 * 16-bit value read from the register.
189 bus_write_2(sc->sc_mem_res, off, val);
204 sc->sc_error = ENXIO;
209 sc->sc_error = ENXIO;
214 /* Register access ready - transaction complete basically. */
216 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) {
218 sc->sc_con_reg | I2C_CON_STP);
226 if (sc->sc_buffer->flags & IIC_M_RD) {
230 * Receive draining interrupt - last data received.
231 * The set FIFO threshold won't be reached to trigger
239 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
242 * Receive data ready interrupt - FIFO has reached the
243 * set threshold.
247 amount = min(sc->sc_fifo_trsh,
248 sc->sc_buffer->len - sc->sc_buffer_pos);
253 sc->sc_buffer->buf[sc->sc_buffer_pos++] =
265 * Transmit draining interrupt - FIFO level is below
266 * the set threshold and the amount of data still to
267 * be transferred won't reach the set FIFO threshold.
275 amount = sc->sc_buffer->len - sc->sc_buffer_pos;
278 * Transmit data ready interrupt - the FIFO level
279 * is below the set threshold.
283 amount = min(sc->sc_fifo_trsh,
284 sc->sc_buffer->len - sc->sc_buffer_pos);
290 sc->sc_buffer->buf[sc->sc_buffer_pos++]);
302 * ti_i2c_intr - interrupt handler for the I2C module
338 if (sc->sc_buffer != NULL)
342 sc->sc_error = EINVAL;
354 * ti_i2c_transfer - called to perform the transfer
378 while (sc->sc_bus_inuse == 1)
379 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0);
382 sc->sc_bus_inuse = 1;
387 sc->sc_buffer = &msgs[i];
388 sc->sc_buffer_pos = 0;
389 sc->sc_error = 0;
392 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL ||
393 sc->sc_buffer->len == 0) {
416 if (sc->sc_buffer->flags & IIC_M_NOSTOP)
423 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len);
430 reg = sc->sc_con_reg | I2C_CON_STT;
433 if ((sc->sc_buffer->flags & IIC_M_RD) == 0)
438 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout);
440 err = sc->sc_error;
456 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
458 sc->sc_buffer = NULL;
459 sc->sc_bus_inuse = 0;
494 * speed. This lets us get the hardware initialized enough to attach
500 if (sc->sc_iicbus == NULL)
503 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
511 * 23.1.4.3 - HS I2C Software Reset
516 sc->sc_con_reg = 0;
517 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
520 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST);
541 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
556 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc);
562 * (see Table 23-8).
564 scll = clkcfg->scll & I2C_SCLL_MASK;
565 sclh = clkcfg->sclh & I2C_SCLH_MASK;
572 * Table 23-8).
581 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) {
582 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT;
583 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT;
584 sc->sc_con_reg |= I2C_CON_OPMODE_HS;
600 * Note: For a 10-bit address, set the corresponding expand Own Address
607 * 7. Set the TX threshold (in transmitter mode) and the RX threshold
609 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX
610 * threshold - 1), where the TX and RX thresholds are greater than
613 * The threshold is set to 5 for now.
615 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK;
623 * 23.1.5.1.1.1.2 - Initialize the I2C Controller
635 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST;
636 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
705 * ti_i2c_deactivate - deactivates the controller and releases resources
711 * Assumed called in an atomic context.
721 /* Disable the controller - cancel all transactions. */
727 if (sc->sc_irq_h != NULL) {
728 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
729 sc->sc_irq_h = NULL;
733 if (sc->sc_mem_res != NULL) {
734 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
735 sc->sc_mem_res = NULL;
739 if (sc->sc_irq_res != NULL) {
740 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
741 sc->sc_irq_res = NULL;
784 val = sc->sc_timeout;
789 if ((err == 0) && (req->newptr != NULL)) {
791 sc->sc_timeout = val;
804 if (!ofw_bus_is_compatible(dev, "ti,omap4-i2c"))
821 sc->sc_dev = dev;
825 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
827 if (sc->sc_mem_res == NULL) {
834 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
836 if (sc->sc_irq_res == NULL) {
837 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
852 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;
860 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz);
862 /* Set the FIFO threshold to 5 for now. */
863 sc->sc_fifo_trsh = 5;
866 sc->sc_timeout = 5*hz;
879 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
880 NULL, ti_i2c_intr, sc, &sc->sc_irq_h);
885 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {