Lines Matching +full:proc +full:- +full:supply
1 /*-
29 * Nvidia Integrated PCI/PCI-Express controller driver.
36 #include <sys/proc.h>
233 #define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)->pads_mem_res, (_r), (_v))
234 #define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r))
235 #define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v))
236 #define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r))
266 "avddio-pex-supply",
267 "dvddio-pex-supply",
268 "avdd-pex-pll-supply",
269 "hvdd-pex-supply",
270 "hvdd-pex-pll-e-supply",
271 "vddio-pex-ctl-supply",
272 "avdd-pll-erefe-supply",
285 "avdd-pll-uerefe-supply",
286 "hvddio-pex-supply",
287 "dvddio-pex-supply",
288 "dvdd-pex-pll-supply",
289 "hvdd-pex-pll-e-supply",
290 "vddio-pex-ctl-supply",
303 {"nvidia,tegra124-pcie", (uintptr_t)&tegra124_soc},
304 {"nvidia,tegra210-pcie", (uintptr_t)&tegra210_soc},
380 irq = intr_map_clone_irq(rman_get_start(sc->irq_res));
395 offs = sc->cfg_base_addr;
398 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs))
400 if (sc->cfg_handle != 0)
401 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800);
408 rv = bus_space_map(sc->bus_tag, offs, 0x800, flags, &sc->cfg_handle);
410 device_printf(sc->dev, "Cannot map config space\n");
412 sc->cfg_cur_offs = offs;
431 if ((sc->ports[i] != NULL) &&
432 (sc->ports[i]->port_idx == slot)) {
433 hndl = sc->ports[i]->cfg_handle;
444 hndl = sc->cfg_handle;
448 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
480 if ((sc->ports[i] != NULL) &&
481 (sc->ports[i]->port_idx == slot)) {
482 hndl = sc->ports[i]->cfg_handle;
493 hndl = sc->cfg_handle;
499 bus_space_write_4(sc->bus_tag, hndl, off, val);
502 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
505 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2);
508 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
511 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2);
521 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
522 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE);
523 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0);
531 /* -----------------------------------------------------------------------
579 /* --------------------------------------------------------------------------
592 offs = tgi->irq / AFI_MSI_INTR_IN_REG;
593 bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG);
614 tf = curthread->td_intr_frame;
620 bit = ffs(reg) - 1;
624 tgi = &sc->isrcs[irq];
625 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) {
628 device_printf(sc->dev,
644 sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF,
647 name = device_get_nameunit(sc->dev);
649 sc->isrcs[irq].irq = irq;
650 error = intr_isrc_register(&sc->isrcs[irq].isrc,
651 sc->dev, 0, "%s,%u", name, irq);
655 if (intr_msi_register(sc->dev,
656 OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0)
670 device_printf(sc->dev, "%s: not implemented yet\n", __func__);
696 /* MSI interrupts are edge trigered -> do nothing */
716 if (data == NULL || data->type != INTR_MAP_DATA_MSI)
719 if (isrc->isrc_handlers == 0)
735 if (isrc->isrc_handlers == 0)
752 mtx_lock(&sc->mtx);
755 for (irq = 0; (irq + count - 1) < TEGRA_PCIB_MAX_MSI; irq++) {
757 if ((irq & (maxcount - 1)) != 0)
766 if ((sc->isrcs[end_irq].flags & TEGRA_FLAG_MSI_USED) ==
778 if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) {
779 mtx_unlock(&sc->mtx);
785 sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED;
787 mtx_unlock(&sc->mtx);
790 srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i];
804 mtx_lock(&sc->mtx);
808 KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED,
809 ("%s: Trying to release an unused MSI-X interrupt",
812 ti->flags &= ~TEGRA_FLAG_MSI_USED;
814 mtx_unlock(&sc->mtx);
825 *addr = vtophys(sc->msi_page);
826 *data = ti->irq;
831 /* ------------------------------------------------------------------- */
852 rv = hwreset_assert(sc->hwreset_pcie_x);
854 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n");
857 rv = hwreset_assert(sc->hwreset_afi);
859 device_printf(sc->dev, "Cannot assert 'afi' reset\n");
862 rv = hwreset_assert(sc->hwreset_pex);
864 device_printf(sc->dev, "Cannot assert 'pex' reset\n");
871 for (i = 0; i < nitems(sc->regulators); i++) {
872 if (sc->regulators[i] == NULL)
874 rv = regulator_enable(sc->regulators[i]);
876 device_printf(sc->dev,
878 sc->soc->regulator_names[i]);
884 sc->clk_pex, sc->hwreset_pex);
886 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n");
890 rv = hwreset_deassert(sc->hwreset_afi);
892 device_printf(sc->dev, "Cannot unreset 'afi' reset\n");
896 rv = clk_enable(sc->clk_afi);
898 device_printf(sc->dev, "Cannot enable 'afi' clock\n");
901 if (sc->soc->cml_clk) {
902 rv = clk_enable(sc->clk_cml);
904 device_printf(sc->dev, "Cannot enable 'cml' clock\n");
908 rv = clk_enable(sc->clk_pll_e);
910 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n");
930 port->enabled = 1;
932 port->enabled = 0;
934 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp));
936 device_printf(sc->dev, "Cannot parse assigned-address: %d\n",
940 port->rp_base_addr = tmp[2];
941 port->rp_size = tmp[4];
942 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1;
943 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) {
944 device_printf(sc->dev, "Invalid port index: %d\n",
945 port->port_idx);
948 /* XXX - TODO:
950 * - it have PCI bus format
951 * - its relative to matching "assigned-addresses"
955 device_printf(sc->dev, "Cannot parse reg: %d\n", rv);
958 port->rp_base_addr += tmp[2];
960 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes,
961 sizeof(port->num_lanes));
962 if (rv != sizeof(port->num_lanes)) {
963 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n",
967 if (port->num_lanes > 4) {
968 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n",
969 port->num_lanes);
973 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx);
974 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx);
977 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy);
979 device_printf(sc->dev,
980 "Cannot get 'pcie-0' phy for port %d\n",
981 port->port_idx);
999 for (i = 0; sc->soc->regulator_names[i] != NULL; i++) {
1000 if (i >= nitems(sc->regulators)) {
1001 device_printf(sc->dev,
1005 rv = regulator_get_by_ofw_property(sc->dev, 0,
1006 sc->soc->regulator_names[i], sc->regulators + i);
1008 device_printf(sc->dev,
1010 sc->soc->regulator_names[i]);
1016 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex);
1018 device_printf(sc->dev, "Cannot get 'pex' reset\n");
1021 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi);
1023 device_printf(sc->dev, "Cannot get 'afi' reset\n");
1026 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x);
1028 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n");
1033 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex);
1035 device_printf(sc->dev, "Cannot get 'pex' clock\n");
1038 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi);
1040 device_printf(sc->dev, "Cannot get 'afi' clock\n");
1043 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e);
1045 device_printf(sc->dev, "Cannot get 'pll_e' clock\n");
1048 if (sc->soc->cml_clk) {
1049 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml);
1051 device_printf(sc->dev, "Cannot get 'cml' clock\n");
1057 sc->num_ports = 0;
1061 device_printf(sc->dev, "Cannot parse PCIe port node\n");
1064 sc->ports[sc->num_ports++] = port;
1079 if (sc->io_range.size != 0) {
1080 device_printf(sc->dev,
1084 sc->io_range = ranges[i];
1089 if (sc->pref_mem_range.size != 0) {
1090 device_printf(sc->dev,
1095 sc->pref_mem_range = ranges[i];
1097 if (sc->mem_range.size != 0) {
1098 device_printf(sc->dev,
1103 sc->mem_range = ranges[i];
1107 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0)
1108 || (sc->pref_mem_range.size == 0)) {
1109 device_printf(sc->dev,
1127 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
1131 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0,
1134 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) {
1135 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
1144 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) {
1145 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
1164 port = sc->ports[port_num];
1167 reg = AFI_RD4(sc, port->afi_pex_ctrl);
1169 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1170 AFI_RD4(sc, port->afi_pex_ctrl);
1177 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1178 AFI_RD4(sc, port->afi_pex_ctrl);
1183 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1185 if (sc->soc->pca_enable) {
1186 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
1189 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0,
1195 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n",
1196 port->port_idx, port->num_lanes,
1197 port->num_lanes > 1 ? "s": "",
1207 port = sc->ports[port_num];
1210 reg = AFI_RD4(sc, port->afi_pex_ctrl);
1212 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1213 AFI_RD4(sc, port->afi_pex_ctrl);
1219 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1222 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n",
1223 port->port_idx, port->num_lanes,
1224 port->num_lanes > 1 ? "s": "");
1253 device_printf(sc->dev, "Cannot enable FDT resources\n");
1269 if (sc->lanes_cfg == 0x14) {
1271 device_printf(sc->dev,
1274 } else if (sc->lanes_cfg == 0x12) {
1276 device_printf(sc->dev,
1280 device_printf(sc->dev,
1281 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg);
1285 if ((sc->ports[i] != NULL))
1287 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx);
1297 if (sc->ports[i] != NULL) {
1298 rv = phy_enable(sc->ports[i]->phy);
1300 device_printf(sc->dev,
1302 sc->ports[i]->port_idx);
1309 PADS_WR4(sc, PADS_REFCLK_CFG0, sc->soc->pads_refclk_cfg0);
1310 if (sc->num_ports > 2)
1311 PADS_WR4(sc, PADS_REFCLK_CFG1, sc->soc->pads_refclk_cfg1);
1313 rv = hwreset_deassert(sc->hwreset_pcie_x);
1315 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n");
1350 /* BAR 0 - type 1 extended configuration. */
1351 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res),
1352 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0);
1354 /* BAR 1 - downstream I/O. */
1355 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO,
1356 sc->io_range.size, 0);
1358 /* BAR 2 - downstream prefetchable memory 1:1. */
1359 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host,
1360 sc->pref_mem_range.host, sc->pref_mem_range.size, 1);
1362 /* BAR 3 - downstream not prefetchable memory 1:1 .*/
1363 tegra_pcib_set_bar(sc, 3, sc->mem_range.host,
1364 sc->mem_range.host, sc->mem_range.size, 1);
1366 /* BAR 3-8 clear. */
1373 /* MSI BAR - clear. */
1388 sc->msi_page = (uintptr_t)kmem_alloc_contig(PAGE_SIZE, M_WAITOK, 0,
1392 tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page),
1400 rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1401 tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie);
1430 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
1431 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller");
1448 sc->dev = dev;
1449 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF);
1452 sc->soc = (struct pcie_soc *)ofw_bus_search_compatible(dev,
1453 compat_data)->ocd_data;
1463 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1465 if (sc->pads_mem_res == NULL) {
1471 * XXX - FIXME
1474 sc->bus_tag = rman_get_bustag(sc->pads_mem_res);
1477 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1479 if (sc->afi_mem_res == NULL) {
1486 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1488 if (sc->cfg_mem_res == NULL) {
1493 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res);
1497 if (sc->ports[i] == NULL)
1499 port = sc->ports[i];
1500 rv = bus_space_map(sc->bus_tag, port->rp_base_addr,
1501 port->rp_size, 0, &port->cfg_handle);
1503 device_printf(sc->dev, "Cannot allocate memory for "
1514 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1516 if (sc->irq_res == NULL) {
1523 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1525 if (sc->irq_res == NULL) {
1531 sc->ofw_pci.sc_range_mask = 0x3;
1536 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range,
1537 sc->ofw_pci.sc_nrange);
1541 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1542 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) {
1555 if (sc->ports[i] == NULL)
1557 if (sc->ports[i]->enabled)
1598 /* MSI/MSI-X */