Lines Matching +full:irqs +full:- +full:map +full:- +full:range
1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 2010-2015 Semihalf
40 * Marvell integrated PCI/PCI-Express controller driver.
87 * Code and data related to fdt-based PCI configuration.
90 * always Marvell-specific so that was deleted and the code now lives here.
103 mv_pci_range_dump(struct mv_pci_range *range)
107 printf(" base_pci = 0x%08lx\n", range->base_pci);
108 printf(" base_par = 0x%08lx\n", range->base_parent);
109 printf(" len = 0x%08lx\n", range->len);
187 if ((par_addr_cells - offset_cells) > 2) {
191 pci_space->base_parent = fdt_data_get((void *)rangesptr,
192 par_addr_cells - offset_cells);
193 rangesptr += par_addr_cells - offset_cells;
199 pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
202 pci_space->base_pci = cell2;
204 if (pci_space->len == 0) {
205 pci_space->len = PCI_SPACE_LEN;
206 pci_space->base_parent = fdt_immr_va +
243 devmap->pd_va = (io_va ? io_va : io_space.base_parent);
244 devmap->pd_pa = io_space.base_parent;
245 devmap->pd_size = io_space.len;
248 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent);
249 devmap->pd_pa = mem_space.base_parent;
250 devmap->pd_size = mem_space.len;
436 OF_parent(node), "marvell,armada-370-pcie")))
442 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
455 sc->sc_dev = self;
460 if (OF_getencprop(node, "marvell,pcie-port", &(port_id),
463 if (!OF_hasprop(node, "marvell,pcie-port"))
469 sc->ap_segment = port_id;
472 sc->sc_type = MV_TYPE_PCIE;
473 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
474 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
475 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
476 sc->sc_skip_enable_procedure = 1;
477 } else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) {
478 sc->sc_type = MV_TYPE_PCIE;
479 sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id);
480 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id);
481 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id);
482 sc->sc_enable_find_root_slot = 1;
484 sc->sc_type = MV_TYPE_PCI;
485 sc->sc_win_target = MV_WIN_PCI_TARGET;
486 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
487 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
492 * Retrieve our mem-mapped registers range.
494 sc->sc_rid = 0;
495 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
497 if (sc->sc_res == NULL) {
498 device_printf(self, "could not map memory\n");
501 sc->sc_bst = rman_get_bustag(sc->sc_res);
502 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
504 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL);
505 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT :
511 if (sc->sc_mode == MV_MODE_ROOT)
512 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t));
544 sc->sc_busnr = bus; /* update bus number */
550 if (sc->sc_mode == MV_MODE_ROOT) {
551 err = mv_pcib_init(sc, sc->sc_busnr,
552 mv_pcib_maxslots(sc->sc_dev));
558 sc->sc_devnr = 1;
559 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
564 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF);
570 rman_fini(&sc->sc_mem_rman);
571 rman_fini(&sc->sc_io_rman);
582 if (sc->sc_skip_enable_procedure)
588 if ((sc->sc_skip_enable_procedure == 0) &&
594 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
598 timeout -= 1000;
599 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
605 if (sc->sc_mode == MV_MODE_ROOT) {
609 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
612 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
624 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
625 err = rman_init(&sc->sc_mem_rman);
629 sc->sc_io_rman.rm_type = RMAN_ARRAY;
630 err = rman_init(&sc->sc_io_rman);
632 rman_fini(&sc->sc_mem_rman);
636 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
637 sc->sc_mem_base + sc->sc_mem_size - 1);
641 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
642 sc->sc_io_base + sc->sc_io_size - 1);
649 rman_fini(&sc->sc_mem_rman);
650 rman_fini(&sc->sc_io_rman);
656 pcib_bit_get(uint32_t *map, uint32_t bit)
661 return (map[n] & (1 << bit));
665 pcib_bit_set(uint32_t *map, uint32_t bit)
670 map[n] |= (1 << bit);
674 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
679 if (pcib_bit_get(map, i))
686 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
691 pcib_bit_set(map, i);
695 * The idea of this allocator is taken from ARM No-Cache memory
701 uint32_t bits, bits_limit, i, *map, min_alloc, size;
706 base = sc->sc_io_base;
708 bits_limit = sc->sc_io_size / min_alloc;
709 map = sc->sc_io_map;
712 base = sc->sc_mem_base;
714 bits_limit = sc->sc_mem_size / min_alloc;
715 map = sc->sc_mem_map;
723 if (pcib_map_check(map, i, bits)) {
724 pcib_map_set(map, i, bits);
745 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
746 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
750 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
755 return (-1);
761 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
763 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
776 io_base = sc->sc_io_base;
777 io_limit = io_base + sc->sc_io_size - 1;
778 mem_base = sc->sc_mem_base;
779 mem_limit = mem_base + sc->sc_mem_size - 1;
782 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
784 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
786 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
788 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
792 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
794 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
798 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
800 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
802 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
804 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
807 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
823 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
832 command = mv_pcib_read_config(sc->sc_dev, bus, slot,
835 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
846 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
849 /* Handle PCI-PCI bridges */
850 class = mv_pcib_read_config(sc->sc_dev, bus, slot,
852 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
883 device_printf(sc->sc_dev,
899 return (&sc->sc_io_rman);
901 return (&sc->sc_mem_rman);
918 return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start,
926 start = sc->sc_mem_base;
927 end = sc->sc_mem_base + sc->sc_mem_size - 1;
928 count = sc->sc_mem_size;
931 if ((start < sc->sc_mem_base) || (start + count - 1 != end) ||
932 (end > sc->sc_mem_base + sc->sc_mem_size - 1))
951 return (pci_domain_adjust_bus(sc->ap_segment, child, r, start,
968 return (pci_domain_release_bus(sc->ap_segment, child, res));
984 return (pci_domain_activate_bus(sc->ap_segment, child, r));
1000 return (pci_domain_deactivate_bus(sc->ap_segment, child, r));
1008 struct resource_map_request *argsp, struct resource_map *map)
1032 map->r_bustag = fdtbus_bs_tag;
1033 map->r_bushandle = start;
1034 map->r_size = length;
1040 struct resource_map *map)
1058 *result = sc->sc_busnr;
1075 sc->sc_busnr = value;
1086 if (sc->sc_type != MV_TYPE_PCIE)
1089 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
1110 ca = (sc->sc_type != MV_TYPE_PCI) ?
1112 cd = (sc->sc_type != MV_TYPE_PCI) ?
1118 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
1123 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
1127 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
1131 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
1145 ca = (sc->sc_type != MV_TYPE_PCI) ?
1147 cd = (sc->sc_type != MV_TYPE_PCI) ?
1153 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
1157 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
1161 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
1165 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
1177 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
1187 if (!sc->sc_enable_find_root_slot)
1205 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
1219 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
1244 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1266 dev = sc->sc_dev;
1274 error = decode_win_cpu_set(sc->sc_win_target,
1275 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0);
1281 error = decode_win_cpu_set(sc->sc_win_target,
1282 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len,
1290 sc->sc_io_base = io_space.base_parent;
1291 sc->sc_io_size = io_space.len;
1293 sc->sc_mem_base = mem_space.base_parent;
1294 sc->sc_mem_size = mem_space.len;
1306 if (!sc->sc_msi_supported)
1309 irq = irq - MSI_IRQ;
1312 if (isclr(&sc->sc_msi_bitmap, irq)) {
1327 int maxcount __unused, int *irqs)
1333 if (!sc->sc_msi_supported)
1339 mtx_lock(&sc->sc_msi_mtx);
1343 if (isset(&sc->sc_msi_bitmap, i))
1351 mtx_unlock(&sc->sc_msi_mtx);
1356 setbit(&sc->sc_msi_bitmap, i);
1357 *irqs++ = MSI_IRQ + i;
1361 mtx_unlock(&sc->sc_msi_mtx);
1366 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
1372 if(!sc->sc_msi_supported)
1375 mtx_lock(&sc->sc_msi_mtx);
1378 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ);
1380 mtx_unlock(&sc->sc_msi_mtx);