Lines Matching +full:no +full:- +full:unaligned +full:- +full:direct +full:- +full:access
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 #define STACKALIGNBYTES (8 - 1)
79 * armv4 and v5 require alignment to the type's size. armv6 requires 8-byte
81 * armv7 requires that an 8-byte type be aligned to at least a 4-byte boundary;
82 * access to smaller types can be unaligned, except that the compiler may
83 * optimize access to adjacent uint32_t values into a single load/store-multiple
84 * instruction which requires 4-byte alignment, so we must provide the most-
87 #define ALIGNED_POINTER(p, t) ((((unsigned)(p)) & (sizeof(t)-1)) == 0)
90 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
98 #define PAGE_MASK (PAGE_SIZE - 1)
102 #define PDRMASK (NBPDR - 1)
103 #define NPDEPG (1 << (32 - PDR_SHIFT))