1 /*-
28  * Vybrid Family 12-bit Analog to Digital Converter (ADC)
53 #define	ADC_HC0		0x00		/* Ctrl reg for hardware triggers */
54 #define	ADC_HC1		0x04		/* Ctrl reg for hardware triggers */
57 #define	 HC_ADCH_S	0		/* Input Channel Select Shift */
61 #define	ADC_R0		0x0C		/* Data result reg for HW triggers */
62 #define	ADC_R1		0x10		/* Data result reg for HW triggers */
66 #define	 CFG_AVGS_S	14		/* Hardware Average select Shift */
69 #define	 CFG_REFSEL_S	11		/* Voltage Reference Select Shift */
73 #define	 CFG_ADLPC	(1 << 7)	/* Low-Power Configuration */
78 #define	 CFG_MODE_S	2		/* Conversion Mode Selection Shift */
79 #define	 CFG_MODE_12	0x2		/* 12-bit mode */
81 #define	 CFG_ADICLK_S	0		/* Input Clock Select Shift */
97 #define	 CV_CV2_S	16		/* Compare Value 2 Shift */
99 #define	 CV_CV1_S	0		/* Compare Value 1 Shift */
103 #define	 OFS_S		0		/* Offset value Shift */
106 #define	 CAL_CODE_S	0		/* Calibration Result Value Shift */
121 	{ -1, 0 }
131 	if (!ofw_bus_is_compatible(dev, "fsl,mvf600-adc"))  in adc_probe()
135 	    "12-bit Analog to Digital Converter");  in adc_probe()
162 	int reg;  in adc_enable()  local
168 	reg = READ4(sc, ADC_HC0);  in adc_enable()
169 	reg &= ~(HC_ADCH_M << HC_ADCH_S);  in adc_enable()
170 	reg |= (channel << HC_ADCH_S);  in adc_enable()
171 	WRITE4(sc, ADC_HC0, reg);  in adc_enable()
181 	int reg;  in adc_attach()  local
185 	if (bus_alloc_resources(dev, adc_spec, sc->res)) {  in adc_attach()
191 	sc->bst = rman_get_bustag(sc->res[0]);  in adc_attach()
192 	sc->bsh = rman_get_bushandle(sc->res[0]);  in adc_attach()
197 	err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE,  in adc_attach()
198 	    NULL, adc_intr, sc, &sc->ih);  in adc_attach()
204 	/* Configure 12-bit mode */  in adc_attach()
205 	reg = READ4(sc, ADC_CFG);  in adc_attach()
206 	reg &= ~(CFG_MODE_M << CFG_MODE_S);  in adc_attach()
207 	reg |= (CFG_MODE_12 << CFG_MODE_S); /* 12bit */  in adc_attach()
208 	WRITE4(sc, ADC_CFG, reg);  in adc_attach()
211 	reg = READ4(sc, ADC_GC);  in adc_attach()
212 	reg |= (GC_ADCO | GC_AVGE);  in adc_attach()
213 	WRITE4(sc, ADC_GC, reg);  in adc_attach()
216 	reg = READ4(sc, ADC_HC0);  in adc_attach()
217 	reg &= HC_AIEN;  in adc_attach()
218 	WRITE4(sc, ADC_HC0, reg);  in adc_attach()