1 /*-
28  * Pin mux and pad control driver for imx5 and imx6.
34  * configures the pins for each device which has a pinctrl-0 property and whose
39  * easy.  Instead of representing each pin and pad configuration using symbolic
40  * properties such as pullup-enable="true" and so on, the data simply contains
77 	{"fsl,imx8mq-iomuxc",	true},
78 	{"fsl,imx6dl-iomuxc",	true},
79 	{"fsl,imx6q-iomuxc",	true},
80 	{"fsl,imx6sl-iomuxc",	true},
81 	{"fsl,imx6ul-iomuxc",	true},
82 	{"fsl,imx6sx-iomuxc",	true},
83 	{"fsl,imx53-iomuxc",	true},
84 	{"fsl,imx51-iomuxc",	true},
100 #define	PADCONF_NONE	(1U << 31)	/* Do not configure pad. */
108 	return (bus_read_4(sc->mem_res, off));  in RD4()
115 	bus_write_4(sc->mem_res, off, val);  in WR4()
121 	u_int select, mask, shift, width;  in iomux_configure_input()  local
130 	 *      | 0xff | shift | width | select |  in iomux_configure_input()
131 	 * We need to mask out the old select value and OR in the new, using a  in iomux_configure_input()
135 		select = val & 0x000000ff;  in iomux_configure_input()
138 		mask  = ((1u << width) - 1) << shift;  in iomux_configure_input()
139 		val = (RD4(sc, reg) & ~mask) | (select << shift);  in iomux_configure_input()
162 		sion = (cfg->padconf_val & PADCONF_SION) ? PADMUX_SION : 0;  in iomux_configure_pins()
163 		WR4(sc, cfg->mux_reg, cfg->mux_val | sion);  in iomux_configure_pins()
164 		iomux_configure_input(sc, cfg->input_reg, cfg->input_val);  in iomux_configure_pins()
165 		if ((cfg->padconf_val & PADCONF_NONE) == 0)  in iomux_configure_pins()
166 			WR4(sc, cfg->padconf_reg, cfg->padconf_val);  in iomux_configure_pins()
173 			    name, cfg->mux_reg, cfg->mux_val | sion,  in iomux_configure_pins()
174 			    cfg->input_reg, cfg->input_val,  in iomux_configure_pins()
175 			    cfg->padconf_reg, cfg->padconf_val);  in iomux_configure_pins()
189 	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)  in iomux_probe()
211 	sc->dev = dev;  in iomux_attach()
215 		sc->last_gpregaddr = 1 * sizeof(uint32_t);  in iomux_attach()
218 		sc->last_gpregaddr = 2 * sizeof(uint32_t);  in iomux_attach()
224 		sc->last_gpregaddr = 13 * sizeof(uint32_t);  in iomux_attach()
227 		sc->last_gpregaddr = 14 * sizeof(uint32_t);  in iomux_attach()
235 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,  in iomux_attach()
237 	if (sc->mem_res == NULL) {  in iomux_attach()
247 	 * pinctrl-0 property cells whose xref phandle refers to a configuration  in iomux_attach()
251 	 * pinctrl device itself may have a pinctrl-0 property which contains  in iomux_attach()
269 	KASSERT(regaddr >= 0 && regaddr <= sc->last_gpregaddr,   in imx_iomux_gpr_get()
271 	    sc->last_gpregaddr));  in imx_iomux_gpr_get()
283 	KASSERT(regaddr >= 0 && regaddr <= sc->last_gpregaddr,   in imx_iomux_gpr_set()
285 	    sc->last_gpregaddr));  in imx_iomux_gpr_set()
298 	KASSERT(regaddr >= 0 && regaddr <= sc->last_gpregaddr,   in imx_iomux_gpr_set_masked()
300 	    sc->last_gpregaddr));  in imx_iomux_gpr_set_masked()