Lines Matching +full:imx21 +full:- +full:i2c
1 /*-
2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk
33 * I2C driver for Freescale i.MX hardware.
36 * This driver currently implements only master-mode operations.
38 * This driver supports multi-master i2c buses, by detecting bus arbitration
41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller
81 #define I2C_ADDR_REG 0x00 /* I2C slave address register */
82 #define I2C_FDR_REG 0x04 /* I2C frequency divider register */
83 #define I2C_CONTROL_REG 0x08 /* I2C control register */
84 #define I2C_STATUS_REG 0x0C /* I2C status register */
85 #define I2C_DATA_REG 0x10 /* I2C data register */
86 #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */
133 {"fsl,imx21-i2c", 1},
134 {"fsl,imx6q-i2c", 1},
135 {"fsl,imx-i2c", 1},
156 if ((lvl) <= (sc)->debug) \
157 device_printf((sc)->dev, fmt, ##args)
160 if ((lvl) <= (sc)->debug) \
219 bus_write_1(sc->res, off, val);
226 return (bus_read_1(sc->res, off));
239 /* Wait for bus to become busy or not-busy. */
246 while (retry --) {
265 * to do clock-stretching so the actual transfer time can be larger, but
269 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0);
272 while (retry --) {
290 * - Clear master mode (MSTA and MTX).
291 * - Wait for the bus to become free or for a timeout to happen.
292 * - Disable the controller.
312 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active);
320 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value);
328 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active);
337 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value);
349 * recovery sequence if necessary, then configure the pins back to i2c
352 if (sc->rb_pinctl_idx == 0)
355 fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx);
364 fdt_pinctrl_configure(sc->dev, 0);
376 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
379 device_set_desc(dev, "Freescale i.MX I2C");
393 sc->dev = dev;
394 sc->rid = 0;
397 if (clk_get_by_ofw_index(sc->dev, 0, 0, &sc->ipgclk) != 0) {
402 err = clk_enable(sc->ipgclk);
404 device_printf(sc->dev, "could not enable ipg clock\n");
409 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
411 if (sc->res == NULL) {
416 sc->iicbus = device_add_child(dev, "iicbus", DEVICE_UNIT_ANY);
417 if (sc->iicbus == NULL) {
422 /* Set up debug-enable sysctl. */
423 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
424 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
425 OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0,
433 node = ofw_bus_get_node(sc->dev);
435 err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios",
436 &sc->rb_sclpin);
439 err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios",
440 &sc->rb_sdapin);
447 * the pinmux config from i2c to gpio.
449 gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT);
450 gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT);
451 gpio_pin_set_active(sc->rb_sclpin, true);
452 gpio_pin_set_active(sc->rb_sdapin, true);
457 * default pinctrl-0. If sc->rb_pinctl_idx is non-zero, the reset code
460 err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx);
462 snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx);
463 if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr))
464 sc->rb_pinctl_idx = cfgidx;
485 error = clk_disable(sc->ipgclk);
487 device_printf(sc->dev, "could not disable ipg clock\n");
492 if ((error = bus_generic_detach(sc->dev)) != 0) {
493 device_printf(sc->dev, "cannot detach child devices\n");
497 /* Release bus-recover pins; gpio_pin_release() handles NULL args. */
498 gpio_pin_release(sc->rb_sclpin);
499 gpio_pin_release(sc->rb_sdapin);
501 if (sc->res != NULL)
502 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res);
527 sc->slave = slave;
528 DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", sc->slave);
551 sc->slave = slave;
552 DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", sc->slave);
566 * Invoke the low-level code to put the bus into master mode and address
569 * addressing the slave is the only operation that a low-level driver
592 DEVICE_DEBUGF(sc, 2, "stop 0x%02x\n", sc->slave);
615 err = clk_get_freq(sc->ipgclk, &freq);
617 device_printf(sc->dev, "cannot get frequency\n");
624 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
634 * pause() while waiting for transfer-complete. With a 66MHz IPG clock
635 * and the actual i2c bus speeds that leads to, for nominal 100KHz and
639 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq);
650 * isn't hung, this a fairly fast no-op.
664 DEVICE_DEBUGF(sc, 1, "read 0x%02x len %d: ", sc->slave, len);
684 if (*read == len - 2) {
688 } else if (*read == len - 1) {
715 DEVICE_DEBUGF(sc, 1, "write 0x%02x len %d: ", sc->slave, len);