Lines Matching full:irq
118 struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */
181 u_int irq;
201 irq = daf->cells[0];
202 if (irq >= sc->gpio_npins) {
203 device_printf(sc->dev, "Invalid interrupt number %u\n", irq);
227 *irqp = irq;
237 u_int irq;
239 irq = dag->gpio_pin_num;
240 if (irq >= sc->gpio_npins) {
241 device_printf(sc->dev, "Invalid interrupt number %u\n", irq);
258 *irqp = irq;
286 u_int irq;
290 error = gpio_pic_map(sc, data, &irq, NULL);
292 *isrcp = &sc->gpio_pic_irqsrc[irq].gi_isrc;
324 u_int icfg, irq, reg, shift, wrk;
334 error = gpio_pic_map(sc, data, &irq, &mode);
337 if (gi->gi_irq != irq)
353 SET4(sc, IMX_GPIO_EDGE_REG, (1u << irq));
355 CLEAR4(sc, IMX_GPIO_EDGE_REG, (1u << irq));
373 if (irq < 16) {
375 shift = 2 * irq;
378 shift = 2 * (irq - 16);
385 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq));
386 SET4(sc, IMX_GPIO_IMR_REG, (1u << irq));
399 u_int irq;
402 irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
405 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq));
416 u_int irq;
419 irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
422 SET4(sc, IMX_GPIO_IMR_REG, (1U << irq));
430 u_int irq;
433 irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
437 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));
444 u_int irq;
447 irq = ((struct gpio_irqsrc *)isrc)->gi_irq;
451 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));
480 device_printf(sc->dev, "Stray irq %u disabled\n", i);
494 uint32_t irq;
498 for (irq = 0; irq < NGPIO; irq++) {
499 sc->gpio_pic_irqsrc[irq].gi_irq = irq;
500 sc->gpio_pic_irqsrc[irq].gi_mode = GPIO_INTR_CONFORM;
502 error = intr_isrc_register(&sc->gpio_pic_irqsrc[irq].gi_isrc,
503 sc->dev, 0, "%s,%u", name, irq);
800 int i, irq, unit;
837 for (irq = 0; irq < 2; irq++) {
839 if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK,
840 gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) {
877 int irq;
894 for (irq = 0; irq < NUM_IRQRES; irq++) {
895 if (sc->gpio_ih[irq])
896 bus_teardown_intr(dev, sc->sc_res[irq + FIRST_IRQRES],
897 sc->gpio_ih[irq]);