Lines Matching +full:anatop +full:- +full:delay +full:- +full:reg +full:- +full:offset
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 * kitchen-sinked this device, not us. :)
45 * I have no idea where the "anatop" name comes from. It's in the standard DTS
46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes
52 * are deci-Celsius, which are converted to/from deci-Kelvins in the sysctl
81 { -1, 0 }
136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
141 #define TZ_ZEROC 2731 /* deci-Kelvin <-> deci-Celsius offset. */
144 imx6_anatop_read_4(bus_size_t offset)
149 return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset));
153 imx6_anatop_write_4(bus_size_t offset, uint32_t value)
158 bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value);
165 uint32_t delay, pmureg;
184 newtarg = (mv - 700) / 25;
190 * (1150-700/25=18).
196 * long conservative delay. After that we need to delay 3uS for every
197 * 25mV step upward; we actually delay 6uS because empirically, it works
199 * going from 400->1200, but works for smaller changes).
205 delay = (newtarg - oldtarg) * 6;
207 delay = 0;
209 delay = (700 / 25) * 6;
225 DELAY(delay);
226 sc->cpu_curmv = newtarg * 25 + 700;
234 return ((sc->refosc_mhz * (plldiv / 2)) / (corediv + 1));
243 *plldiv = ((*corediv + 1) * cpu_mhz) / (sc->refosc_mhz / 2);
260 if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable)
261 cpu_newmhz = sc->cpu_maxmhz_hw;
266 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz);
281 if (op->mhz > sc->cpu_curmhz) {
282 vdd_set(sc, op->mv);
288 * - Set the bypass clock source to REF_CLK_24M (source #0).
289 * - Set the PLL into bypass mode; cpu should now be running at 24mhz.
290 * - Change the divisor.
291 * - Wait for the LOCK bit to come on; it takes ~50 loop iterations.
292 * - Turn off bypass mode; cpu should now be running at the new speed.
294 cpufreq_mhz_to_div(sc, op->mhz, &corediv, &plldiv);
308 if (--timeout == 0)
316 if (op->mhz < sc->cpu_curmhz)
317 vdd_set(sc, op->mv);
318 sc->cpu_curmhz = op->mhz;
322 cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2);
335 temp = sc->cpu_minmhz;
337 if (err != 0 || req->newptr == NULL)
341 if (op->mhz > sc->cpu_maxmhz)
343 else if (op->mhz == sc->cpu_minmhz)
350 sc->cpu_minmhz = op->mhz;
351 if (sc->cpu_minmhz > sc->cpu_curmhz) {
367 temp = sc->cpu_maxmhz;
369 if (err != 0 || req->newptr == NULL)
373 if (op->mhz < sc->cpu_minmhz)
375 else if (op->mhz == sc->cpu_maxmhz)
384 sc->cpu_maxmhz = op->mhz;
397 OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0,
411 OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0,
416 &sc->cpu_overclock_enable, 0,
420 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm
424 sc->refosc_mhz = 24;
430 * - 2b'11: 1200000000Hz;
431 * - 2b'10: 996000000Hz;
432 * - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
433 * - 2b'00: 792000000Hz;
438 sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed];
439 sc->cpu_maxmhz = sc->cpu_maxmhz_hw;
441 TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz);
442 op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz);
443 sc->cpu_minmhz = op->mhz;
444 sc->cpu_minmv = op->mv;
446 TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz);
447 op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz);
448 sc->cpu_maxmhz = op->mhz;
449 sc->cpu_maxmv = op->mv;
466 return (((sc->temp_high_val - (count - sc->temp_high_cnt) *
467 (sc->temp_high_val - 250) /
468 (sc->temp_room_cnt - sc->temp_high_cnt))));
475 return ((sc->temp_room_cnt - sc->temp_high_cnt) *
476 (sc->temp_high_val - temp) / (sc->temp_high_val - 250) +
477 sc->temp_high_cnt);
488 sc->temp_last_cnt =
501 t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC;
513 temp = sc->temp_throttle_val + TZ_ZEROC;
517 temp -= TZ_ZEROC;
518 if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val)
522 sc->temp_throttle_val = temp;
523 sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val);
524 sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100);
528 (sc->temp_throttle_trigger_cnt <<
537 if (sc->cpu_curmhz < sc->cpu_maxmhz) {
538 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz));
546 if (sc->cpu_curmhz > sc->cpu_minmhz) {
547 cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz));
572 if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt)
574 else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt))
577 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
592 sc->temp_room_cnt = (cal & 0xFFF00000) >> 20;
593 sc->temp_high_cnt = (cal & 0x000FFF00) >> 8;
594 sc->temp_high_val = (cal & 0x000000FF) * 10;
600 sc->temp_throttle_val = sc->temp_high_val - 100;
601 sc->temp_throttle_trigger_cnt =
602 temp_to_count(sc, sc->temp_throttle_val);
603 sc->temp_throttle_reset_cnt =
604 temp_to_count(sc, sc->temp_throttle_val - 50);
612 (sc->temp_throttle_trigger_cnt <<
617 * XXX Note that the alarm-interrupt feature isn't working yet, so
622 while (sc->temp_last_cnt == 0)
624 sc->temp_throttle_delay = 100 * SBT_1MS;
625 callout_init(&sc->temp_throttle_callout, 0);
626 callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
648 sc->res[IRQRES] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid,
650 if (sc->res[IRQRES] != NULL) {
651 bus_setup_intr(sc->dev, sc->res[IRQRES],
653 &sc->temp_intrhand);
655 device_printf(sc->dev, "Cannot allocate IRQ resource\n");
657 config_intrhook_disestablish(&sc->intr_setup_hook);
673 if (!sc->cpu_init_done && bus_get_pass() >= cpu_init_pass) {
674 sc->cpu_init_done = true;
678 device_printf(sc->dev, "CPU %uMHz @ %umV\n",
679 sc->cpu_curmhz, sc->cpu_curmv);
700 sc->dev = dev;
703 if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) {
709 sc->intr_setup_hook.ich_func = intr_setup;
710 sc->intr_setup_hook.ich_arg = sc;
711 config_intrhook_establish(&sc->intr_setup_hook);
713 SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev),
714 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
716 &sc->cpu_curmv, 0, "Current CPU voltage in millivolts");
729 * Some day, when we're ready to deal with the actual anatop regulators
740 bus_release_resources(dev, imx6_anatop_spec, sc->res);
749 int reg;
756 reg = (IMX6_ANALOG_CCM_PLL_AUDIO_ENABLE);
757 reg &= ~(IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_MASK << \
759 reg |= (mfi << IMX6_ANALOG_CCM_PLL_AUDIO_DIV_SELECT_SHIFT);
760 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_AUDIO, reg);
774 if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0)