Lines Matching defs:gpio_pic_irqsrc

352 	struct gpio_irqsrc 	*gpio_pic_irqsrc;
1222 		if (!sc->gpio_pic_irqsrc[irq].enabled)
1225 		reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_STA(sc->gpio_pic_irqsrc[irq].bank));
1226 		if (!(reg & (1 << sc->gpio_pic_irqsrc[irq].intnum)))
1229 		isrc = &sc->gpio_pic_irqsrc[irq].isrc;
1260 	sc->gpio_pic_irqsrc = malloc(sizeof(*sc->gpio_pic_irqsrc) * nirqs,
1266 		sc->gpio_pic_irqsrc[nirqs].pin = pin;
1267 		sc->gpio_pic_irqsrc[nirqs].bank = sc->conf->padconf->pins[pin].eint_bank;
1268 		sc->gpio_pic_irqsrc[nirqs].intnum = sc->conf->padconf->pins[pin].eint_num;
1269 		sc->gpio_pic_irqsrc[nirqs].intfunc = sc->conf->padconf->pins[pin].eint_func;
1270 		sc->gpio_pic_irqsrc[nirqs].irq = nirqs;
1271 		sc->gpio_pic_irqsrc[nirqs].mode = GPIO_INTR_CONFORM;
1273 		err = intr_isrc_register(&sc->gpio_pic_irqsrc[nirqs].isrc,
1296 	reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));
1297 	reg &= ~(1 << sc->gpio_pic_irqsrc[irq].intnum);
1298 	AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);
1300 	sc->gpio_pic_irqsrc[irq].enabled = false;
1325 	reg = AW_GPIO_READ(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank));
1326 	reg |= 1 << sc->gpio_pic_irqsrc[irq].intnum;
1327 	AW_GPIO_WRITE(sc, AW_GPIO_GP_INT_CTL(sc->gpio_pic_irqsrc[irq].bank), reg);
1330 	sc->gpio_pic_irqsrc[irq].enabled = true;
1343 		if (sc->gpio_pic_irqsrc[pin].pin == irq)
1390 		*isrcp = &sc->gpio_pic_irqsrc[irq].isrc;
1419 	pinidx = (sc->gpio_pic_irqsrc[irq].intnum % 8) * 4;
1441 	sc->gpio_pic_irqsrc[irq].oldfunc = aw_gpio_get_function(sc,
1442 	    sc->gpio_pic_irqsrc[irq].pin);
1443 	aw_gpio_set_function(sc, sc->gpio_pic_irqsrc[irq].pin,
1444 	    sc->gpio_pic_irqsrc[irq].intfunc);
1448 	    AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,
1449 	    sc->gpio_pic_irqsrc[irq].intnum));
1453 	    AW_GPIO_GP_INT_CFG(sc->gpio_pic_irqsrc[irq].bank,
1454 	    sc->gpio_pic_irqsrc[irq].intnum),