Lines Matching defs:vlapic
54 #include "vlapic.h"
62 #define x2apic(vlapic) (((vlapic)->msr_apicbase & APICBASE_X2APIC) ? 1 : 0)
65 * The 'vlapic->timer_mtx' is used to provide mutual exclusion between the
70 #define VLAPIC_TIMER_LOCK(vlapic) mtx_lock_spin(&((vlapic)->timer_mtx))
71 #define VLAPIC_TIMER_UNLOCK(vlapic) mtx_unlock_spin(&((vlapic)->timer_mtx))
72 #define VLAPIC_TIMER_LOCKED(vlapic) mtx_owned(&((vlapic)->timer_mtx))
81 static void vlapic_set_error(struct vlapic *, uint32_t, bool);
83 static void vlapic_reset(struct vlapic *vlapic);
86 vlapic_get_id(struct vlapic *vlapic)
89 if (x2apic(vlapic))
90 return (vlapic->vcpuid);
92 return (vlapic->vcpuid << 24);
96 x2apic_ldr(struct vlapic *vlapic)
101 apicid = vlapic_get_id(vlapic);
108 vlapic_dfr_write_handler(struct vlapic *vlapic)
112 lapic = vlapic->apic_page;
113 if (x2apic(vlapic)) {
114 VM_CTR1(vlapic->vm, "ignoring write to DFR in x2apic mode: %#x",
124 VLAPIC_CTR0(vlapic, "vlapic DFR in Flat Model");
126 VLAPIC_CTR0(vlapic, "vlapic DFR in Cluster Model");
128 VLAPIC_CTR1(vlapic, "DFR in Unknown Model %#x", lapic->dfr);
132 vlapic_ldr_write_handler(struct vlapic *vlapic)
136 lapic = vlapic->apic_page;
139 if (x2apic(vlapic)) {
140 VLAPIC_CTR1(vlapic, "ignoring write to LDR in x2apic mode: %#x",
142 lapic->ldr = x2apic_ldr(vlapic);
145 VLAPIC_CTR1(vlapic, "vlapic LDR set to %#x", lapic->ldr);
150 vlapic_id_write_handler(struct vlapic *vlapic)
158 lapic = vlapic->apic_page;
159 lapic->id = vlapic_get_id(vlapic);
198 vlapic_get_ccr(struct vlapic *vlapic)
205 lapic = vlapic->apic_page;
207 VLAPIC_TIMER_LOCK(vlapic);
208 if (callout_active(&vlapic->callout)) {
214 if (bintime_cmp(&vlapic->timer_fire_bt, &bt_now, >)) {
215 bt_rem = vlapic->timer_fire_bt;
217 ccr += bt_rem.sec * BT2FREQ(&vlapic->timer_freq_bt);
218 ccr += bt_rem.frac / vlapic->timer_freq_bt.frac;
223 VLAPIC_CTR2(vlapic, "vlapic ccr_timer = %#x, icr_timer = %#x",
225 VLAPIC_TIMER_UNLOCK(vlapic);
230 vlapic_dcr_write_handler(struct vlapic *vlapic)
235 lapic = vlapic->apic_page;
236 VLAPIC_TIMER_LOCK(vlapic);
239 VLAPIC_CTR2(vlapic, "vlapic dcr_timer=%#x, divisor=%d",
248 FREQ2BT(VLAPIC_BUS_FREQ / divisor, &vlapic->timer_freq_bt);
249 vlapic->timer_period_bt = vlapic->timer_freq_bt;
250 bintime_mul(&vlapic->timer_period_bt, lapic->icr_timer);
252 VLAPIC_TIMER_UNLOCK(vlapic);
256 vlapic_esr_write_handler(struct vlapic *vlapic)
260 lapic = vlapic->apic_page;
261 lapic->esr = vlapic->esr_pending;
262 vlapic->esr_pending = 0;
266 vlapic_set_intr_ready(struct vlapic *vlapic, int vector, bool level)
274 lapic = vlapic->apic_page;
276 VLAPIC_CTR1(vlapic, "vlapic is software disabled, ignoring "
282 vlapic_set_error(vlapic, APIC_ESR_RECEIVE_ILLEGAL_VECTOR,
284 VLAPIC_CTR1(vlapic, "vlapic ignoring interrupt to vector %d",
289 if (vlapic->ops.set_intr_ready)
290 return ((*vlapic->ops.set_intr_ready)(vlapic, vector, level));
300 * the vlapic TMR registers.
304 VLAPIC_CTR3(vlapic, "vlapic TMR[%d] is 0x%08x but "
309 VLAPIC_CTR_IRR(vlapic, "vlapic_set_intr_ready");
314 vlapic_get_lvtptr(struct vlapic *vlapic, uint32_t offset)
316 struct LAPIC *lapic = vlapic->apic_page;
368 vlapic_get_lvt(struct vlapic *vlapic, uint32_t offset)
374 val = atomic_load_acq_32(&vlapic->lvt_last[idx]);
379 vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset)
385 lapic = vlapic->apic_page;
386 lvtptr = vlapic_get_lvtptr(vlapic, offset);
409 atomic_store_rel_32(&vlapic->lvt_last[idx], val);
413 vlapic_mask_lvts(struct vlapic *vlapic)
415 struct LAPIC *lapic = vlapic->apic_page;
418 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_CMCI_LVT);
421 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_TIMER_LVT);
424 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_THERM_LVT);
427 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_PERF_LVT);
430 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT0_LVT);
433 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT1_LVT);
436 vlapic_lvt_write_handler(vlapic, APIC_OFFSET_ERROR_LVT);
440 vlapic_fire_lvt(struct vlapic *vlapic, u_int lvt)
444 reg = atomic_load_acq_32(&vlapic->lvt_last[lvt]);
454 vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR,
458 if (vlapic_set_intr_ready(vlapic, vec, false))
459 vcpu_notify_event(vlapic->vcpu, true);
462 vm_inject_nmi(vlapic->vcpu);
465 vm_inject_extint(vlapic->vcpu);
476 dump_isrvec_stk(struct vlapic *vlapic)
481 isrptr = &vlapic->apic_page->isr0;
485 for (i = 0; i <= vlapic->isrvec_stk_top; i++)
486 printf("isrvec_stk[%d] = %d\n", i, vlapic->isrvec_stk[i]);
495 vlapic_update_ppr(struct vlapic *vlapic)
505 isrvec = vlapic->isrvec_stk[vlapic->isrvec_stk_top];
506 tpr = vlapic->apic_page->tpr;
513 if (vlapic->isrvec_stk_top == 0 && isrvec != 0)
521 for (i = 1; i <= vlapic->isrvec_stk_top; i++) {
522 curprio = PRIO(vlapic->isrvec_stk[i]);
524 dump_isrvec_stk(vlapic);
535 isrptr = &vlapic->apic_page->isr0;
539 if (i > vlapic->isrvec_stk_top ||
540 vlapic->isrvec_stk[i] != vector) {
541 dump_isrvec_stk(vlapic);
555 vlapic->apic_page->ppr = ppr;
556 VLAPIC_CTR1(vlapic, "vlapic_update_ppr 0x%02x", ppr);
560 vlapic_sync_tpr(struct vlapic *vlapic)
562 vlapic_update_ppr(vlapic);
568 vlapic_process_eoi(struct vlapic *vlapic)
570 struct LAPIC *lapic = vlapic->apic_page;
581 if (vlapic->isrvec_stk_top <= 0) {
582 panic("invalid vlapic isrvec_stk_top %d",
583 vlapic->isrvec_stk_top);
587 VLAPIC_CTR1(vlapic, "EOI vector %d", vector);
588 VLAPIC_CTR_ISR(vlapic, "vlapic_process_eoi");
589 vlapic->isrvec_stk_top--;
590 vlapic_update_ppr(vlapic);
592 vioapic_process_eoi(vlapic->vm, vector);
597 VLAPIC_CTR0(vlapic, "Gratuitous EOI");
598 vmm_stat_incr(vlapic->vcpu, VLAPIC_GRATUITOUS_EOI, 1);
609 vlapic_periodic_timer(struct vlapic *vlapic)
613 lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT);
618 static VMM_STAT(VLAPIC_INTR_ERROR, "error interrupts generated by vlapic");
621 vlapic_set_error(struct vlapic *vlapic, uint32_t mask, bool lvt_error)
624 vlapic->esr_pending |= mask;
633 if (vlapic_fire_lvt(vlapic, APIC_LVT_ERROR)) {
634 vmm_stat_incr(vlapic->vcpu, VLAPIC_INTR_ERROR, 1);
638 static VMM_STAT(VLAPIC_INTR_TIMER, "timer interrupts generated by vlapic");
641 vlapic_fire_timer(struct vlapic *vlapic)
644 KASSERT(VLAPIC_TIMER_LOCKED(vlapic), ("vlapic_fire_timer not locked"));
646 if (vlapic_fire_lvt(vlapic, APIC_LVT_TIMER)) {
647 VLAPIC_CTR0(vlapic, "vlapic timer fired");
648 vmm_stat_incr(vlapic->vcpu, VLAPIC_INTR_TIMER, 1);
653 "corrected machine check interrupts generated by vlapic");
656 vlapic_fire_cmci(struct vlapic *vlapic)
659 if (vlapic_fire_lvt(vlapic, APIC_LVT_CMCI)) {
660 vmm_stat_incr(vlapic->vcpu, VLAPIC_INTR_CMC, 1);
668 vlapic_trigger_lvt(struct vlapic *vlapic, int vector)
671 if (vlapic_enabled(vlapic) == false) {
679 vm_inject_extint(vlapic->vcpu);
682 vm_inject_nmi(vlapic->vcpu);
698 if (vlapic_fire_lvt(vlapic, vector)) {
699 vmm_stat_array_incr(vlapic->vcpu, LVTS_TRIGGERRED,
710 vlapic_callout_reset(struct vlapic *vlapic, sbintime_t t)
712 callout_reset_sbt_curcpu(&vlapic->callout, t, 0,
713 vlapic_callout_handler, vlapic, 0);
719 struct vlapic *vlapic;
723 vlapic = arg;
725 VLAPIC_TIMER_LOCK(vlapic);
726 if (callout_pending(&vlapic->callout)) /* callout was reset */
729 if (!callout_active(&vlapic->callout)) /* callout was stopped */
732 callout_deactivate(&vlapic->callout);
734 vlapic_fire_timer(vlapic);
736 if (vlapic_periodic_timer(vlapic)) {
738 KASSERT(bintime_cmp(&btnow, &vlapic->timer_fire_bt, >=),
739 ("vlapic callout at %#lx.%#lx, expected at %#lx.#%lx",
740 btnow.sec, btnow.frac, vlapic->timer_fire_bt.sec,
741 vlapic->timer_fire_bt.frac));
748 bintime_sub(&bt, &vlapic->timer_fire_bt);
750 rem_sbt = bttosbt(vlapic->timer_period_bt);
751 if (bintime_cmp(&bt, &vlapic->timer_period_bt, <)) {
763 vlapic->timer_fire_bt = btnow;
764 VLAPIC_CTR2(vlapic, "vlapic timer lagging by %lu "
767 bttosbt(vlapic->timer_period_bt) / SBT_1US);
770 bintime_add(&vlapic->timer_fire_bt, &vlapic->timer_period_bt);
771 vlapic_callout_reset(vlapic, rem_sbt);
774 VLAPIC_TIMER_UNLOCK(vlapic);
778 vlapic_icrtmr_write_handler(struct vlapic *vlapic)
784 VLAPIC_TIMER_LOCK(vlapic);
786 lapic = vlapic->apic_page;
789 vlapic->timer_period_bt = vlapic->timer_freq_bt;
790 bintime_mul(&vlapic->timer_period_bt, icr_timer);
793 binuptime(&vlapic->timer_fire_bt);
794 bintime_add(&vlapic->timer_fire_bt, &vlapic->timer_period_bt);
796 sbt = bttosbt(vlapic->timer_period_bt);
797 vlapic_callout_reset(vlapic, sbt);
799 callout_stop(&vlapic->callout);
801 VLAPIC_TIMER_UNLOCK(vlapic);
815 struct vlapic *vlapic;
865 vlapic = vm_lapic(vm_vcpu(vm, vcpuid));
866 dfr = vlapic->apic_page->dfr;
867 ldr = vlapic->apic_page->ldr;
875 if (x2apic(vlapic)) {
890 VLAPIC_CTR1(vlapic, "vlapic has bad logical "
908 vlapic_set_tpr(struct vlapic *vlapic, uint8_t val)
910 struct LAPIC *lapic = vlapic->apic_page;
913 VLAPIC_CTR2(vlapic, "vlapic TPR changed from %#x to %#x",
916 vlapic_update_ppr(vlapic);
921 vlapic_get_tpr(struct vlapic *vlapic)
923 struct LAPIC *lapic = vlapic->apic_page;
929 vlapic_set_cr8(struct vlapic *vlapic, uint64_t val)
934 vm_inject_gp(vlapic->vcpu);
939 vlapic_set_tpr(vlapic, tpr);
943 vlapic_get_cr8(struct vlapic *vlapic)
947 tpr = vlapic_get_tpr(vlapic);
1032 vlapic_icrlo_write_handler(struct vlapic *vlapic, bool *retu)
1043 lapic = vlapic->apic_page;
1047 if (x2apic(vlapic))
1056 VLAPIC_CTR2(vlapic, "icrlo 0x%016lx triggered ipi %d", icrval, vec);
1060 vlapic_calcdest(vlapic->vm, &dmask, dest, phys, false, x2apic(vlapic));
1063 CPU_SETOF(vlapic->vcpuid, &dmask);
1066 dmask = vm_active_cpus(vlapic->vm);
1069 dmask = vm_active_cpus(vlapic->vm);
1070 CPU_CLR(vlapic->vcpuid, &dmask);
1080 VLAPIC_CTR1(vlapic, "Ignoring invalid ICR %016lx", icrval);
1093 vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR,
1095 VLAPIC_CTR1(vlapic, "Ignoring invalid IPI %d", vec);
1100 vcpu = vm_vcpu(vlapic->vm, i);
1102 vmm_stat_incr(vlapic->vcpu, VLAPIC_IPI_SEND, 1);
1104 VLAPIC_CTR2(vlapic,
1105 "vlapic sending ipi %d to vcpuid %d", vec, i);
1111 vcpu = vm_vcpu(vlapic->vm, i);
1113 VLAPIC_CTR1(vlapic,
1114 "vlapic sending ipi nmi to vcpuid %d", i);
1120 if (!vlapic->ipi_exit) {
1124 i = vm_apicid2vcpuid(vlapic->vm, dest);
1125 if (i >= vm_get_maxcpus(vlapic->vm) ||
1126 i == vlapic->vcpuid)
1141 vmexit = vm_exitinfo(vlapic->vcpu);
1145 *vm_exitinfo_cpuset(vlapic->vcpu) = ipimask;
1156 struct vlapic *vlapic = vm_lapic(vcpu);
1158 vlapic_reset(vlapic);
1164 struct vlapic *vlapic = vm_lapic(vcpu);
1181 if (!vlapic->ipi_exit)
1201 if (!vlapic->ipi_exit) {
1216 vlapic_self_ipi_handler(struct vlapic *vlapic, uint64_t val)
1220 KASSERT(x2apic(vlapic), ("SELF_IPI does not exist in xAPIC mode"));
1223 lapic_intr_edge(vlapic->vcpu, vec);
1224 vmm_stat_incr(vlapic->vcpu, VLAPIC_IPI_SEND, 1);
1225 vmm_stat_incr(vlapic->vcpu, VLAPIC_IPI_RECV, 1);
1226 VLAPIC_CTR1(vlapic, "vlapic self-ipi %d", vec);
1230 vlapic_pending_intr(struct vlapic *vlapic, int *vecptr)
1232 struct LAPIC *lapic = vlapic->apic_page;
1236 vlapic_update_ppr(vlapic);
1238 if (vlapic->ops.pending_intr)
1239 return ((*vlapic->ops.pending_intr)(vlapic, vecptr));
1250 VLAPIC_CTR1(vlapic, "pending intr %d", vector);
1262 vlapic_intr_accepted(struct vlapic *vlapic, int vector)
1264 struct LAPIC *lapic = vlapic->apic_page;
1268 if (vlapic->ops.intr_accepted)
1269 return ((*vlapic->ops.intr_accepted)(vlapic, vector));
1279 VLAPIC_CTR_IRR(vlapic, "vlapic_intr_accepted");
1283 VLAPIC_CTR_ISR(vlapic, "vlapic_intr_accepted");
1288 vlapic->isrvec_stk_top++;
1290 stk_top = vlapic->isrvec_stk_top;
1294 vlapic->isrvec_stk[stk_top] = vector;
1298 vlapic_svr_write_handler(struct vlapic *vlapic)
1303 lapic = vlapic->apic_page;
1306 old = vlapic->svr_last;
1307 vlapic->svr_last = new;
1316 VLAPIC_CTR0(vlapic, "vlapic is software-disabled");
1317 VLAPIC_TIMER_LOCK(vlapic);
1318 callout_stop(&vlapic->callout);
1319 VLAPIC_TIMER_UNLOCK(vlapic);
1320 vlapic_mask_lvts(vlapic);
1326 VLAPIC_CTR0(vlapic, "vlapic is software-enabled");
1327 if (vlapic_periodic_timer(vlapic))
1328 vlapic_icrtmr_write_handler(vlapic);
1334 vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
1337 struct LAPIC *lapic = vlapic->apic_page;
1342 if (x2apic(vlapic) && mmio_access) {
1343 VLAPIC_CTR1(vlapic, "MMIO read from offset %#lx in x2APIC mode",
1349 if (!x2apic(vlapic) && !mmio_access) {
1353 VLAPIC_CTR1(vlapic, "x2APIC MSR read from offset %#lx in "
1374 *data = vlapic_get_tpr(vlapic);
1414 if (x2apic(vlapic))
1422 *data = vlapic_get_lvt(vlapic, offset);
1424 reg = vlapic_get_lvtptr(vlapic, offset);
1433 *data = vlapic_get_ccr(vlapic);
1440 * XXX generate a GP fault if vlapic is in x2apic mode
1450 VLAPIC_CTR2(vlapic, "vlapic read offset %#x, data %#lx", offset, *data);
1455 vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
1458 struct LAPIC *lapic = vlapic->apic_page;
1465 VLAPIC_CTR2(vlapic, "vlapic write offset %#lx, data %#lx",
1472 if (x2apic(vlapic) && mmio_access) {
1473 VLAPIC_CTR2(vlapic, "MMIO write of %#lx to offset %#lx "
1481 if (!x2apic(vlapic) && !mmio_access) {
1482 VLAPIC_CTR2(vlapic, "x2APIC MSR write of %#lx to offset %#lx "
1492 vlapic_id_write_handler(vlapic);
1495 vlapic_set_tpr(vlapic, data & 0xff);
1498 vlapic_process_eoi(vlapic);
1502 vlapic_ldr_write_handler(vlapic);
1506 vlapic_dfr_write_handler(vlapic);
1510 vlapic_svr_write_handler(vlapic);
1514 if (x2apic(vlapic))
1516 retval = vlapic_icrlo_write_handler(vlapic, retu);
1523 regptr = vlapic_get_lvtptr(vlapic, offset);
1525 vlapic_lvt_write_handler(vlapic, offset);
1529 vlapic_icrtmr_write_handler(vlapic);
1534 vlapic_dcr_write_handler(vlapic);
1538 vlapic_esr_write_handler(vlapic);
1542 if (x2apic(vlapic))
1543 vlapic_self_ipi_handler(vlapic, data);
1563 vlapic_reset(struct vlapic *vlapic)
1567 lapic = vlapic->apic_page;
1570 lapic->id = vlapic_get_id(vlapic);
1575 vlapic_mask_lvts(vlapic);
1576 vlapic_reset_tmr(vlapic);
1579 vlapic_dcr_write_handler(vlapic);
1581 vlapic->svr_last = lapic->svr;
1585 vlapic_init(struct vlapic *vlapic)
1587 KASSERT(vlapic->vm != NULL, ("vlapic_init: vm is not initialized"));
1588 KASSERT(vlapic->vcpuid >= 0 &&
1589 vlapic->vcpuid < vm_get_maxcpus(vlapic->vm),
1591 KASSERT(vlapic->apic_page != NULL, ("vlapic_init: apic_page is not "
1595 * If the vlapic is configured in x2apic mode then it will be
1601 mtx_init(&vlapic->timer_mtx, "vlapic timer mtx", NULL, MTX_SPIN);
1602 callout_init(&vlapic->callout, 1);
1604 vlapic->msr_apicbase = DEFAULT_APIC_BASE | APICBASE_ENABLED;
1606 if (vlapic->vcpuid == 0)
1607 vlapic->msr_apicbase |= APICBASE_BSP;
1609 vlapic->ipi_exit = false;
1611 vlapic_reset(vlapic);
1615 vlapic_cleanup(struct vlapic *vlapic)
1618 callout_drain(&vlapic->callout);
1619 mtx_destroy(&vlapic->timer_mtx);
1623 vlapic_get_apicbase(struct vlapic *vlapic)
1626 return (vlapic->msr_apicbase);
1630 vlapic_set_apicbase(struct vlapic *vlapic, uint64_t new)
1633 if (vlapic->msr_apicbase != new) {
1634 VLAPIC_CTR2(vlapic, "Changing APIC_BASE MSR from %#lx to %#lx "
1635 "not supported", vlapic->msr_apicbase, new);
1645 struct vlapic *vlapic;
1648 vlapic = vm_lapic(vcpu);
1651 vlapic->msr_apicbase &= ~APICBASE_X2APIC;
1653 vlapic->msr_apicbase |= APICBASE_X2APIC;
1661 lapic = vlapic->apic_page;
1662 lapic->id = vlapic_get_id(vlapic);
1663 if (x2apic(vlapic)) {
1664 lapic->ldr = x2apic_ldr(vlapic);
1672 if (vlapic->ops.enable_x2apic_mode)
1673 (*vlapic->ops.enable_x2apic_mode)(vlapic);
1689 VM_CTR1(vm, "vlapic intr invalid delmode %#x", delmode);
1712 vlapic_post_intr(struct vlapic *vlapic, int hostcpu, int ipinum)
1723 if (vlapic->ops.post_intr)
1724 (*vlapic->ops.post_intr)(vlapic, hostcpu);
1730 vlapic_enabled(struct vlapic *vlapic)
1732 struct LAPIC *lapic = vlapic->apic_page;
1734 if ((vlapic->msr_apicbase & APICBASE_ENABLED) != 0 &&
1742 vlapic_set_tmr(struct vlapic *vlapic, int vector, bool level)
1748 lapic = vlapic->apic_page;
1757 if (vlapic->ops.set_tmr != NULL)
1758 (*vlapic->ops.set_tmr)(vlapic, vector, level);
1762 vlapic_reset_tmr(struct vlapic *vlapic)
1766 VLAPIC_CTR0(vlapic, "vlapic resetting all vectors to edge-triggered");
1769 vlapic_set_tmr(vlapic, vector, false);
1773 vlapic_set_tmr_level(struct vlapic *vlapic, uint32_t dest, bool phys,
1785 VLAPIC_CTR1(vlapic, "Ignoring level trigger-mode for "
1791 vlapic_calcdest(vlapic->vm, &dmask, dest, phys, lowprio, false);
1793 if (!CPU_ISSET(vlapic->vcpuid, &dmask))
1796 VLAPIC_CTR1(vlapic, "vector %d set to level-triggered", vector);
1797 vlapic_set_tmr(vlapic, vector, true);
1802 vlapic_reset_callout(struct vlapic *vlapic, uint32_t ccr)
1810 VLAPIC_TIMER_LOCK(vlapic);
1812 bt = vlapic->timer_freq_bt;
1816 binuptime(&vlapic->timer_fire_bt);
1817 bintime_add(&vlapic->timer_fire_bt, &bt);
1820 vlapic_callout_reset(vlapic, sbt);
1823 if (vlapic_periodic_timer(vlapic)) {
1824 binuptime(&vlapic->timer_fire_bt);
1825 bintime_add(&vlapic->timer_fire_bt,
1826 &vlapic->timer_period_bt);
1827 sbt = bttosbt(vlapic->timer_period_bt);
1829 callout_stop(&vlapic->callout);
1830 vlapic_callout_reset(vlapic, sbt);
1834 VLAPIC_TIMER_UNLOCK(vlapic);
1842 struct vlapic *vlapic;
1856 vlapic = vm_lapic(vcpu);
1859 lapic = vlapic->apic_page;
1862 SNAPSHOT_VAR_OR_LEAVE(vlapic->esr_pending, meta, ret, done);
1864 SNAPSHOT_VAR_OR_LEAVE(vlapic->timer_freq_bt.sec,
1866 SNAPSHOT_VAR_OR_LEAVE(vlapic->timer_freq_bt.frac,
1874 vlapic->timer_period_bt = vlapic->timer_freq_bt;
1875 bintime_mul(&vlapic->timer_period_bt, lapic->icr_timer);
1878 SNAPSHOT_BUF_OR_LEAVE(vlapic->isrvec_stk,
1879 sizeof(vlapic->isrvec_stk),
1881 SNAPSHOT_VAR_OR_LEAVE(vlapic->isrvec_stk_top, meta, ret, done);
1883 SNAPSHOT_BUF_OR_LEAVE(vlapic->lvt_last,
1884 sizeof(vlapic->lvt_last),
1888 ccr = vlapic_get_ccr(vlapic);
1893 vlapic_enabled(vlapic) && lapic->icr_timer != 0) {
1894 /* Reset the value of the 'timer_fire_bt' and the vlapic
1900 vlapic_reset_callout(vlapic, ccr);