Lines Matching full:bus

33 #include <sys/bus.h>
52 static uint32_t	pci_docfgregread(int domain, int bus, int slot, int func,
54 static struct pcie_mcfg_region *pcie_lookup_region(int domain, int bus);
55 static int	pciereg_cfgread(struct pcie_mcfg_region *region, int bus,
57 static void	pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus,
60 static int	pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
61 static void	pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
90 pcie_lookup_region(int domain, int bus)
94 		    bus >= mcfg_regions[i].minbus &&
95 		    bus <= mcfg_regions[i].maxbus)
101 pci_docfgregread(int domain, int bus, int slot, int func, int reg, int bytes)
103 	if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0)
104 		return (pcireg_cfgread(bus, slot, func, reg, bytes));
109 		region = pcie_lookup_region(domain, bus);
111 			return (pciereg_cfgread(region, bus, slot, func, reg,
116 		return (pcireg_cfgread(bus, slot, func, reg, bytes));
125 pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes)
138 		line = pci_docfgregread(domain, bus, slot, func, PCIR_INTLINE,
144 	return (pci_docfgregread(domain, bus, slot, func, reg, bytes));
151 pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data,
154 	if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0) {
155 		pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
162 		region = pcie_lookup_region(domain, bus);
164 			pciereg_cfgwrite(region, bus, slot, func, reg, data,
171 		pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
180 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
184 	if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX &&
187 		outl(CONF1_ADDR_PORT, (1U << 31) | (bus << 16) | (slot << 11)
206 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
212 	port = pci_cfgenable(bus, slot, func, reg, bytes);
232 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
237 	port = pci_cfgenable(bus, slot, func, reg, bytes);
262 	 * On some AMD systems, some of the devices on bus 0 are
264 	 * bus 0 looking for such devices.  For these devices, we will
289 		printf("PCI: MCFG domain %u bus %u-%u base @ 0x%lx\n",
313 #define PCIE_VADDR(base, reg, bus, slot, func)	\
315 	((((bus) & 0xff) << 20)		|	\
329 pciereg_cfgread(struct pcie_mcfg_region *region, int bus, unsigned slot,
335 	MPASS(bus >= region->minbus && bus <= region->maxbus);
340 	va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func);
361 pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus, unsigned slot,
366 	MPASS(bus >= region->minbus && bus <= region->maxbus);
371 	va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func);