Lines Matching +full:memory +full:- +full:controller
2 EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration,
3 and DMA interfaces that a driver uses to access its PCI controller.
5 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
9 http://opensource.org/licenses/bsd-license.php
54 #define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or …
55 #define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cyc…
56 #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit dec…
57 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater …
59 #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit d…
60 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3…
61 #define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7…
62 #define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377…
63 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are com…
65 #define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the …
67 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w access…
68 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range
69 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device
72 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater …
74 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3…
86 /// A read operation from system memory by a bus master.
90 /// A write operation from system memory by a bus master.
94 /// Provides both read and write access to system memory by both the processor and a
108 /// Retrieve the PCI controller's current attributes, and return them in Result.
112 /// Set the PCI controller's current attributes to Attributes.
116 …/// Enable the attributes specified by the bits that are set in Attributes for this PCI controller.
120 …// Disable the attributes specified by the bits that are set in Attributes for this PCI controller.
124 /// Retrieve the PCI controller's supported attributes, and return them in Result.
131 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
135 @param Width Signifies the width of the memory or I/O operations.
137 base address for the memory operation to perform.
138 @param Offset The offset within the selected BAR to start the memory operation.
142 @param Result Pointer to the last value read from the memory location.
145 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
146 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.
166 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
169 @param Width Signifies the width of the memory or I/O operations.
171 … base address for the memory or I/O operation to perform.
172 …@param Offset The offset within the selected BAR to start the memory or I/O operat…
173 @param Count The number of memory or I/O operations to perform.
177 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
178 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
198 /// Read PCI controller registers in the PCI memory or I/O space.
202 /// Write PCI controller registers in the PCI memory or I/O space.
208 Enable a PCI driver to access PCI controller registers in PCI configuration space.
211 @param Width Signifies the width of the memory operations.
212 …@param Offset The offset within the PCI configuration space for the PCI controller.
218 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
220 valid for the PCI configuration header of the PCI controller.
237 /// Read PCI controller registers in PCI configuration space.
241 /// Write PCI controller registers in PCI configuration space.
247 Enables a PCI driver to copy one region of PCI memory space to another region of PCI
248 memory space.
251 @param Width Signifies the width of the memory operations.
253 base address for the memory operation to perform.
255 start the memory writes for the copy operation.
257 base address for the memory operation to perform.
259 the memory reads for the copy operation.
260 @param Count The number of memory operations to perform. Bytes moved is Width
263 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
264 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.
265 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.
287 Provides the PCI controller-specific addresses needed to access system memory.
290 …aram Operation Indicates if the bus master is going to read or write to system memory.
291 @param HostAddress The system memory address to map to the PCI controller.
294 …@param DeviceAddress The resulting map address for the bus master PCI controller to use to
323 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
339 @param MemoryType The type of memory to allocate, EfiBootServicesData or
342 @param HostAddress A pointer to store the base system memory address of the
346 @retval EFI_SUCCESS The requested memory pages were allocated.
350 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
365 Frees memory that was allocated with AllocateBuffer().
369 …@param HostAddress The base system memory address of the allocated range. …
371 @retval EFI_SUCCESS The requested memory pages were freed.
372 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
385 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
390 bridge to system memory.
402 Retrieves this PCI controller's current PCI bus number, device number, and function number.
405 @param SegmentNumber The PCI controller's current PCI segment number.
406 @param BusNumber The PCI controller's current PCI bus number.
407 @param DeviceNumber The PCI controller's current PCI device number.
408 @param FunctionNumber The PCI controller's current PCI function number.
410 …@retval EFI_SUCCESS The PCI controller location was returned. …
425 Performs an operation on the attributes that this PCI controller supports. The operations include
430 @param Operation The operation to perform on the attributes for this PCI controller.
436 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
439 Attributes are not supported by this PCI controller or one of
453 Gets the attributes that this PCI controller supports setting on a BAR using
459 …@param Supports A pointer to the mask of attributes that this PCI controller supports
462 … configuration of this BAR of the PCI controller.
465 controller supports are returned in Supports. If Resources
467 controller is currently using are returned in Resources.
469 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
484 Sets the attributes for a range of a BAR on a PCI controller.
498 set on the PCI controller, and the actual resource range is returned
501 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
518 /// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration,
520 /// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus.
521 /// A device driver that wishes to manage a PCI controller in a system will have to
522 /// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller.
547 /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible
548 /// for allocating memory for the ROM image, and copying the contents of the ROM to memory.
550 /// through the ROM BAR of the PCI controller, or it is from a platform-specific location.