Lines Matching +full:in +full:- +full:memory
2 EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration,
5 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
9 http://opensource.org/licenses/bsd-license.php
54 #define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or …
55 #define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cyc…
56 #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit dec…
57 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater …
59 #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit d…
60 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3…
61 #define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7…
62 #define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377…
63 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are com…
64 #define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI…
65 #define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the …
66 #define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config…
67 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w access…
68 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range
69 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device
72 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater …
74 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3…
86 /// A read operation from system memory by a bus master.
90 /// A write operation from system memory by a bus master.
94 /// Provides both read and write access to system memory by both the processor and a
108 /// Retrieve the PCI controller's current attributes, and return them in Result.
116 …/// Enable the attributes specified by the bits that are set in Attributes for this PCI controller.
120 …/// Disable the attributes specified by the bits that are set in Attributes for this PCI controlle…
124 /// Retrieve the PCI controller's supported attributes, and return them in Result.
131 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
135 @param Width Signifies the width of the memory or I/O operations.
137 base address for the memory operation to perform.
138 @param Offset The offset within the selected BAR to start the memory operation.
142 @param Result Pointer to the last value read from the memory location.
155 IN EFI_PCI_IO_PROTOCOL *This,
156 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
157 IN UINT8 BarIndex,
158 IN UINT64 Offset,
159 IN UINT64 Mask,
160 IN UINT64 Value,
161 IN UINT64 Delay,
166 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
169 @param Width Signifies the width of the memory or I/O operations.
171 … base address for the memory or I/O operation to perform.
172 …@param Offset The offset within the selected BAR to start the memory or I/O operat…
173 @param Count The number of memory or I/O operations to perform.
188 IN EFI_PCI_IO_PROTOCOL *This,
189 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
190 IN UINT8 BarIndex,
191 IN UINT64 Offset,
192 IN UINTN Count,
193 IN OUT VOID *Buffer
198 /// Read PCI controller registers in the PCI memory or I/O space.
202 /// Write PCI controller registers in the PCI memory or I/O space.
208 Enable a PCI driver to access PCI controller registers in PCI configuration space.
211 @param Width Signifies the width of the memory operations.
228 IN EFI_PCI_IO_PROTOCOL *This,
229 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
230 IN UINT32 Offset,
231 IN UINTN Count,
232 IN OUT VOID *Buffer
237 /// Read PCI controller registers in PCI configuration space.
241 /// Write PCI controller registers in PCI configuration space.
247 Enables a PCI driver to copy one region of PCI memory space to another region of PCI
248 memory space.
251 @param Width Signifies the width of the memory operations.
252 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the
253 base address for the memory operation to perform.
255 start the memory writes for the copy operation.
256 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the
257 base address for the memory operation to perform.
259 the memory reads for the copy operation.
260 @param Count The number of memory operations to perform. Bytes moved is Width
263 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
277 IN EFI_PCI_IO_PROTOCOL *This,
278 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
279 IN UINT8 DestBarIndex,
280 IN UINT64 DestOffset,
281 IN UINT8 SrcBarIndex,
282 IN UINT64 SrcOffset,
283 IN UINTN Count
287 Provides the PCI controller-specific addresses needed to access system memory.
290 …aram Operation Indicates if the bus master is going to read or write to system memory.
291 @param HostAddress The system memory address to map to the PCI controller.
308 IN EFI_PCI_IO_PROTOCOL *This,
309 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
310 IN VOID *HostAddress,
311 IN OUT UINTN *NumberOfBytes,
323 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
329 IN EFI_PCI_IO_PROTOCOL *This,
330 IN VOID *Mapping
339 @param MemoryType The type of memory to allocate, EfiBootServicesData or
342 @param HostAddress A pointer to store the base system memory address of the
346 @retval EFI_SUCCESS The requested memory pages were allocated.
350 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
356 IN EFI_PCI_IO_PROTOCOL *This,
357 IN EFI_ALLOCATE_TYPE Type,
358 IN EFI_MEMORY_TYPE MemoryType,
359 IN UINTN Pages,
361 IN UINT64 Attributes
365 Frees memory that was allocated with AllocateBuffer().
369 …@param HostAddress The base system memory address of the allocated range. …
371 @retval EFI_SUCCESS The requested memory pages were freed.
372 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
379 IN EFI_PCI_IO_PROTOCOL *This,
380 IN UINTN Pages,
381 IN VOID *HostAddress
385 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
390 bridge to system memory.
398 IN EFI_PCI_IO_PROTOCOL *This
417 IN EFI_PCI_IO_PROTOCOL *This,
438 @retval EFI_UNSUPPORTED one or more of the bits set in
446 IN EFI_PCI_IO_PROTOCOL *This,
447 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
448 IN UINT64 Attributes,
465 controller supports are returned in Supports. If Resources
467 controller is currently using are returned in Resources.
477 IN EFI_PCI_IO_PROTOCOL *This,
478 IN UINT8 BarIndex,
499 in Offset and Length.
510 IN EFI_PCI_IO_PROTOCOL *This,
511 IN UINT64 Attributes,
512 IN UINT8 BarIndex,
513 IN OUT UINT64 *Offset,
514 IN OUT UINT64 *Length
518 /// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration,
521 /// A device driver that wishes to manage a PCI controller in a system will have to
542 /// The size, in bytes, of the ROM image.
547 /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible
548 /// for allocating memory for the ROM image, and copying the contents of the ROM to memory.
550 /// through the ROM BAR of the PCI controller, or it is from a platform-specific location.