Lines Matching +full:ras +full:- +full:to +full:- +full:cas

13 .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
40 CPUs contain PMCs conforming to version 2 of the
44 .Bl -tag -width "Li PMC_CLASS_UCP"
46 Fixed-function counters that count only one hardware event per counter.
48 Programmable counters that may be configured to count one of a defined
52 The number of PMCs available in each class and their widths need to be
58 .%B "Intel(R) 64 and IA-32 Architectures Software Developes Manual"
60 .%N "Order Number: 253669-033US"
67 Not all CPUs in this family implement fixed-function counters.
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
87 .Bl -tag -width indent
89 Configure the PMC to increment only if the number of configured
90 events measured in a cycle is greater than or equal to
93 Configure the PMC to count the number of de-asserted to asserted
108 .Bl -tag -width indent
133 The GQ read tracker allocate to deallocate occupancy count is divided by the
134 count to obtain the average read tracker latency.
137 Counts the number of tread tracker allocate to deallocate entries.
138 The GQ read tracker allocate to deallocate occupancy count is divided by
139 the count to obtain the average read tracker latency.
144 The GQ read tracker L3 miss to fill occupancy count is divided by this count
156 The GQ read tracker L3 hit occupancy count is divided by this count to obtain the average L3 hit la…
161 The GQ read tracker L3 miss to RTID acquired occupancy count is
162 divided by this count to obtain the average latency for a read L3 miss to
169 The GQ write tracker L3 miss to RTID occupancy count is divided by this count
170 to obtain the average latency for a write L3 miss to acquire an RTID.
176 is divided by the this count to obtain the average L3 write miss latency.
181 The GQ peer probe occupancy count is divided by this count to obtain the average
209 Cycles GQ QPI and QMC output data port is busy sending data to the Quickpath
214 Cycles GQ L3 output data port is busy sending data to the Last Level Cache.
218 Cycles GQ Core output data port is busy sending data to the Cores.
222 Number of snoop responses to the local home that L3 does not have the
226 Number of snoop responses to the local home that L3 has the referenced line
230 Number of responses to code or data read snoops to the local home that the
232 The L3 cache line state is changed to the S state and the line is forwarded
236 Number of responses to read invalidate snoops to the local home that the L3
238 The L3 cache line state is invalidated and the line is forwarded to the
242 Number of conflict snoop responses sent to the local home.
245 Number of responses to code or data read snoops to the local home that the
249 Number of snoop responses to a remote home that L3 does not have the
253 Number of snoop responses to a remote home that L3 has the referenced line
257 Number of responses to code or data read snoops to a remote home that the L3
259 The L3 cache line state is changed to the S state and the line is forwarded
263 Number of responses to read invalidate snoops to a remote home that the L3
265 The L3 cache line state is invalidated and the line is forwarded to the
269 Number of conflict snoop responses sent to the local home.
272 Number of responses to code or data read snoops to a remote home that the L3
276 Number of HITM snoop responses to a remote home.
283 Writebacks from the cores will always result in L3 hits due to the
297 Should always be zero as writebacks from the cores will always result in L3 hits due to the inclusi…
309 line was forwarded in M state is forwarded due to a Snoop Read Invalidate Own request.
325 When the victim cache line is in M state, the line is written to its home cache agent
432 QHL IOH tracker allocate to deallocate read occupancy.
435 QHL remote tracker allocate to deallocate read occupancy.
438 QHL local tracker allocate to deallocate read occupancy.
468 Counts number or requests to the Quickpath Memory Controller that bypass the
499 read request to DRAM channel 0.
503 read request to DRAM channel 1.
507 read request to DRAM channel 2.
511 write request to DRAM channel 0.
515 write request to DRAM channel 1.
519 write request to DRAM channel 2.
601 Counts number of full cache line writes to DRAM channel 0.
604 Counts number of full cache line writes to DRAM channel 1.
607 Counts number of full cache line writes to DRAM channel 2.
610 Counts number of full cache line writes to DRAM.
613 Counts number of partial cache line writes to DRAM channel 0.
616 Counts number of partial cache line writes to DRAM channel 1.
619 Counts number of partial cache line writes to DRAM channel 2.
622 Counts number of partial cache line writes to DRAM.
640 that has already been issued to the QMC.
641 In this instance, the QHL will send a priority update to QMC to
648 already been issued to the QMC.
649 In this instance, the QHL will send a priority update to QMC to expedite the request.
655 already been issued to the QMC.
656 In this instance, the QHL will send a priority update to QMC to expedite the request.
662 been issued to the QMC.
663 In this instance, the QHL will send a priority update to QMC to expedite the request.
667 DRAM retry only occurs when configured in RAS mode.
671 DRAM retry only occurs when configured in RAS mode.
675 DRAM retry only occurs when configured in RAS mode.
679 DRAM retry only occurs when configured in RAS mode.
683 Home Logic to the IOH.
687 Home Logic to the remote home.
691 Home Logic to the local home.
698 Counts number of occurrences a request was put to sleep due to IOH ordering
700 While in the sleep state, the request is not eligible to be scheduled to the QMC.
703 Counts number of occurrences a request was put to sleep due to remote socket
705 While in the sleep state, the request is not eligible to be scheduled to the QMC.
708 Counts number of occurrences a request was put to sleep due to local socket
710 While in the sleep state, the request is not eligible to be scheduled to the QMC.
713 Counts number of occurrences a request was put to sleep due to IOH address conflicts.
714 While in the sleep state, the request is not eligible to be scheduled to the QMC.
717 Counts number of occurrences a request was put to sleep due to remote socket
719 While in the sleep state, the request is not eligible to be scheduled to the QMC.
722 Counts number of occurrences a request was put to sleep due to local socket address conflicts.
723 While in the sleep state, the request is not eligible to be scheduled to the QMC.
727 qualified by mask value written to MSR 396H.
735 is qualified by mask value written to MSR 396H.
743 is qualified by mask value written to MSR 396H.
751 due to lack of a VNA and VN0 credit.
757 due to lack of a VNA and VN0 credit.
762 Counts cycles the Quickpath outbound link 0 non-data response virtual
763 channel is stalled due to lack of a VNA and VN0 credit.
769 due to lack of a VNA and VN0 credit.
775 due to lack of a VNA and VN0 credit.
780 Counts cycles the Quickpath outbound link 1 non-data response virtual
781 channel is stalled due to lack of a VNA and VN0 credit.
799 stalled due to lack of VNA and VN0 credits.
804 Counts cycles the Quickpath outbound link 0 Non-Coherent Bypass virtual
805 channel is stalled due to lack of VNA and VN0 credits.
810 Counts cycles the Quickpath outbound link 0 Non-Coherent Standard virtual
811 channel is stalled due to lack of VNA and VN0 credits.
817 stalled due to lack of VNA and VN0 credits.
822 Counts cycles the Quickpath outbound link 1 Non-Coherent Bypass virtual
823 channel is stalled due to lack of VNA and VN0 credits.
828 Counts cycles the Quickpath outbound link 1 Non-Coherent Standard virtual
829 channel is stalled due to lack of VNA and VN0 credits.
862 Number of cycles that snoop packets incoming to the Quickpath Interface link
863 0 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT)
867 Number of cycles that snoop packets incoming to the Quickpath Interface link
868 1 are stalled and not sent to the GQ because the GQ Peer Probe Tracker (PPT)
884 DRAM channel 0 command issued to CLOSE a page due to page idle timer expiration.
888 DRAM channel 1 command issued to CLOSE a page due to page idle timer expiration.
892 DRAM channel 2 command issued to CLOSE a page due to page idle timer expiration.
896 Counts the number of precharges (PRE) that were issued to DRAM channel 0
898 A page miss refers to a situation in which a page is currently open and another
899 page from the same bank needs to be opened.
904 Counts the number of precharges (PRE) that were issued to DRAM channel 1
906 A page miss refers to a situation in which a page is currently open and another
907 page from the same bank needs to be opened.
912 Counts the number of precharges (PRE) that were issued to DRAM channel 2
914 A page miss refers to a situation in which a page is currently open and another
915 page from the same bank needs to be opened.
920 Counts the number of times a read CAS command was issued on DRAM channel 0.
923 Counts the number of times a read CAS command was issued on DRAM channel 0
924 where the command issued used the auto-precharge (auto page close) mode.
927 Counts the number of times a read CAS command was issued on DRAM channel 1.
930 Counts the number of times a read CAS command was issued on DRAM channel 1
931 where the command issued used the auto-precharge (auto page close) mode.
934 Counts the number of times a read CAS command was issued on DRAM channel 2.
937 Counts the number of times a read CAS command was issued on DRAM channel 2
938 where the command issued used the auto-precharge (auto page close) mode.
941 Counts the number of times a write CAS command was issued on DRAM channel 0.
944 Counts the number of times a write CAS command was issued on DRAM channel 0
945 where the command issued used the auto-precharge (auto page close) mode.
948 Counts the number of times a write CAS command was issued on DRAM channel 1.
951 Counts the number of times a write CAS command was issued on DRAM channel 1
952 where the command issued used the auto-precharge (auto page close) mode.
955 Counts the number of times a write CAS command was issued on DRAM channel 2.
958 Counts the number of times a write CAS command was issued on DRAM channel 2
959 where the command issued used the auto-precharge (auto page close) mode.
964 In order to keep correct data content, the data values have to be
970 In order to keep correct data content, the data values have to be refreshed periodically.
975 In order to keep correct data content, the data values have to be refreshed periodically.
978 Counts number of DRAM Channel 0 precharge-all (PREALL) commands that close
980 PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode.
983 Counts number of DRAM Channel 1 precharge-all (PREALL) commands that close
985 PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode.
988 Counts number of DRAM Channel 2 precharge-all (PREALL) commands that close
990 PREALL is issued when the DRAM needs to be refreshed or needs to go into a power down mode.
993 Uncore cycles DRAM was throttled due to its temperature being above the
1033 Cycles that the PCU records that core 0 is a low power state due to the
1038 Cycles that the PCU records that core 1 is a low power state due to the
1043 Cycles that the PCU records that core 2 is a low power state due to the
1048 Cycles that the PCU records that core 3 is a low power state due to the